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Rajesh Garg
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2010 – 2019
- 2012
- [c26]Hai Huang, Salman Baset, Chunqiang Tang, Ashu Gupta, K. N. Madhu Sudhan, Fazal Feroze, Rajesh Garg, Sumithra Ravichandran:
Patch management automation for enterprise cloud. NOMS 2012: 691-705
2000 – 2009
- 2009
- [j3]Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan:
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electron. 5(2): 157-172 (2009) - [j2]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electron. 5(2): 185-195 (2009) - [j1]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi:
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 781-792 (2009) - [c25]Rajesh Garg, Sunil P. Khatri:
Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC 2009: 461-467 - [c24]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444 - [c23]Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri:
A robust pulsed flip-flop and its use in enhanced scan design. ICCD 2009: 97-102 - [c22]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD 2009: 131-136 - [c21]Rajesh Garg, Sunil P. Khatri:
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. ICCD 2009: 498-504 - [c20]Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri:
A radiation tolerant Phase Locked Loop design for digital electronics. ICCD 2009: 505-510 - [c19]Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri:
A PLL design based on a standing wave resonant oscillator. ICCD 2009: 511-516 - [c18]Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya:
Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672 - [c17]Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi:
SEU hardened clock regeneration circuits. ISQED 2009: 806-813 - 2008
- [c16]Rajesh Garg, Charu Nagpal, Sunil P. Khatri:
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923 - [c15]Charu Nagpal, Rajesh Garg, Sunil P. Khatri:
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359 - [c14]Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri:
A Single-supply True Voltage Level Shifter. DATE 2008: 979-984 - [c13]Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri:
A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122 - [c12]Suganth Paul, Rajesh Garg, Sunil P. Khatri:
Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218 - [c11]Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng:
A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320 - [c10]Rajesh Garg, Sunil P. Khatri:
A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20 - [c9]Rajesh Garg, Peng Li, Sunil P. Khatri:
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791 - 2007
- [c8]Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri:
A methodology for interconnect dimension determination. ISPD 2007: 189-195 - [c7]Rajesh Garg, Chunjie Duan, Jinyun Zhang, Sinan Gezici:
Low Power UWB Transceiver Design Using Dynamic Voltage Scaling. WCNC 2007: 1757-1762 - 2006
- [c6]Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri:
A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424 - [c5]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi:
A design approach for radiation-hard digital electronics. DAC 2006: 773-778 - [c4]Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222 - [c3]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis. ICCD 2006: 37-42 - [c2]Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006: 76-81 - [c1]Rajesh Garg, Sunil P. Khatri:
Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006
Coauthor Index
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