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Hailong Jiao
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2020 – today
- 2024
- [j30]Changchun Zhou
, Yuzhe Fu
Adjustable Multi-Stream Block-Wise Farthest Point Sampling Acceleration in Point Cloud Analysis. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3523-3527 (2024) - [j29]Yuzhe Fu
SoftAct: A High-Precision Softmax Architecture for Transformers Supporting Nonlinear Functions. IEEE Trans. Circuits Syst. Video Technol. 34(9): 8912-8923 (2024) - [c49]Zhuoya Yan, Yingna Huang, Hailong Jiao:
A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching. ISCAS 2024: 1-5 - 2023
- [j28]Changchun Zhou
Sagitta: An Energy-Efficient Sparse 3D-CNN Accelerator for Real-Time 3-D Understanding. IEEE Internet Things J. 10(23): 20703-20717 (2023) - [j27]Cong Huang
C3MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure. IEEE J. Solid State Circuits 58(10): 2685-2695 (2023) - [j26]Xiaojin Zhao
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4221-4222 (2023) - [j25]Ming Liu, Changchun Zhou
CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow. IEEE Trans. Circuits Syst. Video Technol. 33(12): 7084-7095 (2023) - [j24]Siyuan Qiu
LightSeizureNet: A Lightweight Deep Learning Model for Real-Time Epileptic Seizure Detection. IEEE J. Biomed. Health Informatics 27(4): 1845-1856 (2023) - [c48]Changchun Zhou, Yuzhe Fu
An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling. ICCAD 2023: 1-9 - 2022
- [j23]Adam Cron, Hailong Jiao, Erik Jan Marinissen:
Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. IEEE Des. Test 39(5): 5-6 (2022) - [j22]Paul Detterer
Receiver Design With an Adjustable Energy-Signal-Quality Tradeoff for IoT Networks. IEEE Internet Things J. 9(22): 23086-23096 (2022) - [j21]Jiacong Sun
An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit. IEEE J. Solid State Circuits 57(11): 3477-3489 (2022) - [j20]Hing-Mo Lam
A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 401-414 (2022) - [j19]Xugang Cao
A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 554-558 (2022) - [j18]Yuting Chen, Yuxuan Nie, Hailong Jiao
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 676-680 (2022) - [c47]Chenyu Xie, Chunmei Yang, Hailong Jiao:
A Karnaugh Map Approximate Adder With Intrinsic Error Compensation. APCCAS 2022: 10-14 - [c46]Ming Liu, Yifan He, Hailong Jiao:
An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator. APCCAS 2022: 55-59 - [c45]Xudong Wang, Geng Li, Jiacong Sun
Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks. APCCAS 2022: 246-250 - 2021
- [j17]Paul Detterer
Receiver-Sensitivity Control for Energy-Efficient IoT Networks. IEEE Commun. Lett. 25(4): 1383-1386 (2021) - [j16]Yunbo Huang
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3093-3097 (2021) - [j15]Hing-Mo Lam
Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers. IEEE Trans. Circuits Syst. Video Technol. 31(5): 2056-2062 (2021) - [j14]Kamlesh Singh
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1039-1051 (2021) - [c44]Min Liu, Yifan He, Hailong Jiao:
Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration. AICAS 2021: 1-4 - [c43]Changchun Zhou, Min Liu, Siyuan Qiu, Yifan He, Hailong Jiao:
An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance. DAC 2021: 241-246 - [c42]Kris van Noord, Wenjin Wang, Hailong Jiao:
Insights of 3D Input CNN in EEG-based Emotion Recognition. EMBC 2021: 212-215 - [c41]Hing-Mo Lam, Silin Lu, Hezi Qiu, Hailong Jiao, Min Zhang
Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder. ISCAS 2021: 1-5 - [c40]Silin Lu, Lei Lu, Shengdong Zhang
A Pull-Up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs. ISCAS 2021: 1-5 - [c39]Chen Xu, Xiaolei Su, Zhengkun Shen, Dong Wang, Yi Tan, Zexue Liu, Hailong Jiao, Junhua Liu, Huailin Liao:
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications. ISCAS 2021: 1-5 - 2020
- [j13]Jian Liang, Shuiping Yi, Wenlong Bai, Lidan Wang, Chenchang Zhan, Congwei Liao, Hing-Mo Lam, Min Zhang
A -80 dB PSRR 4.99 ppm/°C TC bandgap reference with nonlinear compensation. Microelectron. J. 95 (2020) - [j12]Yanan Sun
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2431-2441 (2020) - [c38]Paul Detterer
Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. DATE 2020: 1674-1679 - [c37]Hailong Jiao, Zhanliang Zhang:
A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode. ISCAS 2020: 1-5 - [c36]Hezi Qiu, Jian Liang, Wenlong Bai, Hing-Mo Lam, Junjun An, Congwei Liao, Min Zhang
A Compensation System using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c35]Paul Detterer
Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. DATE 2019: 102-107 - [c34]Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC 2019: 1-2 - [c33]Yuting Chen, Hailong Jiao:
Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits. ICICDT 2019: 1-4 - [c32]Jiacong Sun
A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations. ICICDT 2019: 1-4 - [c31]Chunmei Yang, Hailong Jiao:
Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations. ICICDT 2019: 1-4 - [c30]Xinxin Huo, Wenlong Bai, Hing-Mo Lam, Congwei Liao, Min Zhang
A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays. ISCAS 2019: 1-5 - [c29]Kamlesh Singh, Barry de Bruin
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC 2019: 370-375 - 2018
- [j11]Hailong Jiao
Crosstalk-noise-aware bus coding with low-power ground-gated repeaters. Int. J. Circuit Theory Appl. 46(2): 280-289 (2018) - [c28]Luc Waeijen, Hailong Jiao, Henk Corporaal, Yifan He:
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude. DSD 2018: 54-61 - [c27]Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS 2018: 1-6 - [c26]Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS 2018: 1-5 - [c25]Kamlesh Singh, Hailong Jiao, Jos Huisken
Low power latch based design with smart retiming. ISQED 2018: 329-334 - [c24]Fanglei Hu, Min Zhang
Achieving Low Power Classification with Classifier Ensemble. ISVLSI 2018: 16-21 - [c23]Leonidas Katselas, Alkis A. Hatzopoulos
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. ITC 2018: 1-9 - [c22]Paul Detterer
Understanding the Impact of Circuit-Level Inaccuracy on Sensor Network Performance. PE-WASUN 2018: 107-114 - 2017
- [c21]Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON 2017: 908-911 - [c20]Peng Ling, Chong Shen, Kun Zhang, Hailong Jiao, Liqiang Zheng, Xi Deng:
An improved NLOS error elimination algorithm for indoor ultra-wideband localization. IEEE SENSORS 2017: 1-3 - [c19]Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens:
An analytical model for interdependent setup/hold-time characterization of flip-flops. ISQED 2017: 209-214 - [c18]Martin Van Leussen, Jos Huisken
Reconfigurable Support Vector Machine Classifier with Approximate Computing. ISVLSI 2017: 13-18 - [c17]Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. PATMOS 2017: 1-8 - 2016
- [j10]Hailong Jiao, Yongmin Qiu, Volkan Kursun
Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. Integr. 53: 68-79 (2016) - [j9]Hailong Jiao, Yongmin Qiu, Volkan Kursun
Low power and robust memory circuits with asymmetrical ground gating. Microelectron. J. 48: 109-119 (2016) - [c16]Erik Jan Marinissen
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. ETS 2016: 1-10 - [c15]Hailong Jiao, Yongmin Qiu, Volkan Kursun
Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. IOLTS 2016: 39-42 - 2015
- [j8]Yanan Sun, Hailong Jiao, Volkan Kursun
A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1729-1739 (2015) - [c14]Said Hamdioui, Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Henk Corporaal, Hailong Jiao, Francky Catthoor, Dirk J. Wouters, Eike Linn, Jan van Lunteren:
Memristor based computation-in-memory architecture for data-intensive applications. DATE 2015: 1718-1725 - 2014
- [j7]Hailong Jiao, Volkan Kursun
Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits. Microelectron. J. 45(8): 1125-1131 (2014) - [c13]Yanan Sun, Hailong Jiao, Volkan Kursun
Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. ICM 2014: 164-167 - 2013
- [j6]Hailong Jiao, Volkan Kursun
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 533-545 (2013) - [c12]Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. ISCAS 2013: 2331-2334 - [c11]Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. ISQED 2013: 353-358 - [c10]Hailong Jiao, Volkan Kursun
Ground gated 8T SRAM cells with enhanced read and hold data stability. ISVLSI 2013: 52-57 - [c9]Bo Xie, Hailong Jiao, Junbo Wang, Deyong Chen, Jian Chen:
An electrostatically-driven and capacitively-sensed differential lateral resonant pressure microsensor. NEMS 2013: 1271-1274 - [c8]Hailong Jiao, Volkan Kursun
Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits. VLSI-SoC 2013: 150-155 - 2012
- [j5]Hailong Jiao, Volkan Kursun
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 741-745 (2012) - [c7]Hailong Jiao, Volkan Kursun
Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations. ISCAS 2012: 484-487 - [c6]Hailong Jiao, Volkan Kursun
Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits. ISOCC 2012: 466-469 - 2011
- [j4]Hailong Jiao, Volkan Kursun
Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias. J. Circuits Syst. Comput. 20(1): 125-145 (2011) - [j3]Hailong Jiao, Volkan Kursun
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 763-773 (2011) - [c5]Hailong Jiao, Volkan Kursun
Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits. SoCC 2011: 365-370 - 2010
- [j2]Hailong Jiao, Volkan Kursun
Low-Leakage and Compact Registers with Easy-Sleep Mode. J. Low Power Electron. 6(2): 263-279 (2010) - [j1]Hailong Jiao, Volkan Kursun
Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2053-2065 (2010) - [c4]Hailong Jiao, Volkan Kursun
Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops. ISCAS 2010: 3845-3848 - [c3]Hailong Jiao, Volkan Kursun
Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits. VLSI-SoC (Selected Papers) 2010: 258-290 - [c2]Hailong Jiao, Volkan Kursun
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. VLSI-SoC 2010: 347-351
2000 – 2009
- 2008
- [c1]Hailong Jiao, Lan Chen:
Cellwise OPC Based on Reduced Standard Cell Library. ISQED 2008: 810-814
Coauthor Index
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