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Mitsuji Okada
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2020 – today
- 2023
- [j6]Kota Shiba
, Mitsuji Okada, Atsutake Kosuge
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. IEEE J. Solid State Circuits 58(7): 2075-2086 (2023) - [j5]Kota Shiba
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3440-3450 (2023) - 2022
- [c6]Kota Shiba
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. HCS 2022: 1-14 - [c5]Kota Shiba
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS 2022: 99-103
2010 – 2019
- 2019
- [c4]Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda:
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS 2019: 1 - 2015
- [j4]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express 12(4): 20141157 (2015) - [j3]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2600-2606 (2015) - 2014
- [c3]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS 2014: 137-140 - 2012
- [j2]Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno:
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits 47(2): 435-443 (2012) - 2010
- [j1]Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. IEEE J. Solid State Circuits 45(12): 2582-2590 (2010) - [c2]Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. ISSCC 2010: 470-471
2000 – 2009
- 2000
- [c1]Shinichi Kozu, Toshiya Aramaki, Chinatsu Ikeda, Yasuaki Kuroda, Satoru Kawanago, Mitsuji Okada, Hiroshi Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii:
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home. CICC 2000: 231-234
Coauthor Index
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