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Daesun Oh
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2010 – 2019
- 2010
- [j3]Daesun Oh, Keshab K. Parhi
:
Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 105-115 (2010) - [j2]Daesun Oh, Keshab K. Parhi
Low-Complexity Switch Network for Reconfigurable LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 85-94 (2010)
2000 – 2009
- 2009
- [j1]Daesun Oh, Keshab K. Parhi
Low Complexity Decoder Architecture for Low-Density Parity-Check Codes. J. Signal Process. Syst. 56(2-3): 217-228 (2009) - 2008
- [c7]Daesun Oh, Keshab K. Parhi
Optimally quantized offset min-sum algorithm for flexible LDPC decoder. ACSCC 2008: 1886-1891 - [c6]Daesun Oh, Keshab K. Parhi
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes. ACM Great Lakes Symposium on VLSI 2008: 451-456 - [c5]Daesun Oh, Keshab K. Parhi
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. ISCAS 2008: 240-243 - 2007
- [c4]Daesun Oh, Keshab K. Parhi
Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. ISCAS 2007: 1855-1858 - [c3]Daesun Oh, Keshab K. Parhi
Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes. ISCAS 2007: 2758-2761 - 2006
- [c2]Daesun Oh, Keshab K. Parhi
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers. ASAP 2006: 118-124 - [c1]Daesun Oh, Keshab K. Parhi
Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes. SiPS 2006: 262-267
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