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Jeng-Liang Tsai
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2000 – 2009
- 2006
- [j3]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian
, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [c10]Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC 2006: 941-946 - [c9]Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS 2006 - 2005
- [j2]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22(3): 214-222 (2005) - [c8]Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC 2005: 1168-1171 - [c7]Jeng-Liang Tsai, Lizheng Zhang:
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. ICCAD 2005: 575-581 - [c6]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426 - 2004
- [j1]Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 565-572 (2004) - [c5]Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE 2004: 830-835 - [c4]Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik:
HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD 2004: 489-496 - [c3]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618 - [c2]Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 124-131 - 2003
- [c1]Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD 2003: 166-173
Coauthor Index
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