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Jin Yang 0006
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
Other persons with the same name
- Jin Yang — disambiguation page
- Jin Yang 0001 — Technische Universität Ilmenau, Germany
- Jin Yang 0002 — Imperial College London, UK
- Jin Yang 0003
— Aston University, School of Engineering and Applied Science, Birmingham, UK (and 1 more)
- Jin Yang 0004
- Jin Yang 0005 — Hong Kong Polytechnic University, Internet and Mobile Computing Lab
- Jin Yang 0007
- Jin Yang 0008
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2020 – today
- 2024
- [j7]Jin Yang
Correct-by-Construction Design of Custom Accelerator Microarchitectures. IEEE Trans. Computers 73(1): 278-291 (2024) - 2023
- [c33]Yanzhao Wang
An Equivalence Checking Framework for Agile Hardware Design. ASP-DAC 2023: 26-32 - [c32]Jeremy Casas, Zhenkun Yang, Wen Wang, Jin Yang, Adwait Godbole:
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine. DAC 2023: 1-6 - [c31]Jin Yang, Jeremy Casas, Zhenkun Yang:
Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design. DAC 2023: 1-4 - [c30]Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang:
An Automated Verification Framework for HalideIR-Based Compiler Transformations. DATE 2023: 1-6 - [c29]Hanchen Ye
High-level Synthesis for Domain Specific Computing. ISPD 2023: 211-219 - [i6]Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang:
Towards A Correct-by-Construction FHE Model. IACR Cryptol. ePrint Arch. 2023: 281 (2023) - 2022
- [j6]Md Rubel Ahmed
Mining Patterns From Concurrent Execution Traces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2758-2762 (2022) - [c28]Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC 2022: 1351-1354 - 2021
- [j5]David Shia, Jin Yang:
A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors. Microelectron. J. 112: 105058 (2021) - [c27]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System Designs. ICCD 2021: 492-499 - [c26]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. ISQED 2021: 374-380 - [c25]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
A Comparative Study of Specification Mining Methods for SoC Communication Traces. ISVLSI 2021: 31-36 - [i5]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System-on-Chip Designs. CoRR abs/2102.06989 (2021) - [i4]Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang:
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. CoRR abs/2111.15024 (2021) - 2020
- [c24]Zhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer
UEFI Firmware Fuzzing with Simics Virtual Platform. DAC 2020: 1-6 - [c23]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. ISQED 2020: 389-394 - [i3]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. CoRR abs/2005.01574 (2020) - [i2]Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang:
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. CoRR abs/2005.02550 (2020) - [i1]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. CoRR abs/2005.11221 (2020)
2010 – 2019
- 2017
- [c22]Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang:
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. ICCD 2017: 177-184 - 2016
- [c21]Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang:
Protocol-guided analysis of post-silicon traces under limited observability. ISQED 2016: 301-306 - 2015
- [c20]Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia
Correctness and security at odds: post-silicon validation of modern SoC designs. DAC 2015: 146:1-146:6 - 2014
- [c19]Sava Krstic, Jin Yang, David W. Palmer, Randy B. Osborne, Eran Talmor:
Security of SoC firmware load protocols. HOST 2014: 70-75 - [c18]Ranan Fraer, Doron Keren, Zurab Khasidashvili, Alexander Novakovsky, Avi Puder, Eli Singerman, Eran Talmor, Moshe Y. Vardi, Jin Yang:
From visual to logical formalisms for SoC validation. MEMOCODE 2014: 165-174 - 2012
- [j4]Doron Bustan, Dmitry Korchemny, Erik Seligman
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. IEEE Des. Test Comput. 29(2): 23-31 (2012) - [j3]Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1997-2010 (2012) - 2010
- [c17]Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang:
Optimizing equivalence checking for behavioral synthesis. DATE 2010: 1500-1505
2000 – 2009
- 2009
- [c16]Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang:
Formal Verification for High-Assurance Behavioral Synthesis. ATVA 2009: 337-351 - 2008
- [c15]Yan Chen, Fei Xie, Jin Yang:
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. DAC 2008: 143-148 - [c14]Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD 2008: 1-10 - 2007
- [c13]Yan Chen, Yujing He, Fei Xie, Jin Yang:
Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation. FMCAD 2007: 111-118 - 2006
- [j2]William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski:
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1652-1663 (2006) - [c12]Jin Yang:
Verification Challenges and Opportunities in the New Era of Microprocessor Design. ATVA 2006: 6-7 - [c11]Guowu Yang, Jin Yang, Xiaoyu Song, Fei Xie:
Maximal Models of Assertion Graph in GSTE. TAMC 2006: 684-693 - 2005
- [c10]Jin Yang, Avi Puder:
Tightly integrate dynamic verification with formal verification: a GSTE based approach. ASP-DAC 2005: 327-330 - [c9]Xiushan Feng, Alan J. Hu, Jin Yang:
Partitioned model checking from software specifications. ASP-DAC 2005: 583-587 - [c8]Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song:
Implication of assertion graphs in GSTE. ASP-DAC 2005: 1060-1063 - 2004
- [c7]Jin Yang, Carl-Johan H. Seger:
Compositional Specification and Model Checking in GSTE. CAV 2004: 216-228 - [c6]William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski:
Quantum logic synthesis by symbolic reachability analysis. DAC 2004: 838-841 - 2003
- [j1]Jin Yang, Carl-Johan H. Seger:
Introduction to generalized symbolic trajectory evaluation. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 345-353 (2003) - [c5]Alan J. Hu, Jeremy Casas, Jin Yang:
Reasoning about GSTE Assertion Graphs. CHARME 2003: 170-184 - 2002
- [c4]Jin Yang, Carl-Johan H. Seger:
Generalized Symbolic Trajectory Evaluation - Abstraction in Action. FMCAD 2002: 70-87 - [c3]Jin Yang, Amit Goel:
GSTE through a case study. ICCAD 2002: 534-541 - 2001
- [c2]Jin Yang, Carl-Johan H. Seger:
Introduction to Generalized Symbolic Trajectory Evaluation. ICCD 2001: 360-367 - 2000
- [c1]Jin Yang, Andreas Tiemeyer:
Lazy symbolic model checking. DAC 2000: 35-38
Coauthor Index
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