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Kunihiko Iizuka
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2010 – 2019
- 2016
- [j16]Masahiko Maruyama
, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka:
An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise. IEEE J. Solid State Circuits 51(10): 2252-2261 (2016) - [j15]Takeshi Mitsunaka
CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays. IEEE J. Solid State Circuits 51(11): 2534-2544 (2016) - [c9]Takeshi Mitsunaka, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima
28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays. ISSCC 2016: 478-479 - 2015
- [j14]Takeshi Mitsunaka, Kunihiko Iizuka, Minoru Fujishima
97-mW 8-Phase CMOS VCO and Dividers for a 134-GHz PLL Synthesizer. IEICE Trans. Electron. 98-C(7): 685-692 (2015) - [c8]Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka:
A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise. A-SSCC 2015: 1-4 - 2014
- [j13]Takeshi Mitsunaka, Yusuke Kishino, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima
9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 101-108 (2014) - [j12]Takeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima
8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler. IEICE Trans. Electron. 97-C(6): 486-494 (2014) - 2011
- [j11]Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. IEEE J. Solid State Circuits 46(10): 2386-2395 (2011) - 2010
- [j10]Kunihiko Iizuka:
Foreword. IEICE Trans. Electron. 93-C(6): 717 (2010) - [c7]Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. ISSCC 2010: 144-145
2000 – 2009
- 2009
- [j9]Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka:
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. IEEE J. Solid State Circuits 44(6): 1697-1708 (2009) - 2008
- [j8]Kunihiko Iizuka, Masato Koutani, Takeshi Mitsunaka, Hiroshi Kawamura, Shinji Toyoyama, Masayuki Miyamoto, Akira Matsuzawa:
RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers. IEICE Trans. Electron. 91-C(6): 854-861 (2008) - 2007
- [j7]Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno:
A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor. IEEE J. Solid State Circuits 42(4): 862-871 (2007) - [j6]Masato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka:
A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers. IEEE J. Solid State Circuits 42(11): 2395-2403 (2007) - [c6]Takae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka:
A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. ISSCC 2007: 212-597 - 2006
- [j5]Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito:
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. IEEE J. Solid State Circuits 41(4): 883-890 (2006) - [j4]Mutsuo Daito, Hirofumi Matsui, Masaya Ueda, Kunihiko Iizuka:
A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration. IEEE J. Solid State Circuits 41(11): 2417-2423 (2006) - [c5]Koutani Kagoshima, Shuichi Kawama, Shinji Toyoyama, Kunihiko Iizuka:
Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration. CICC 2006: 837-840 - 2005
- [c4]Masato Koutani, Kunihiko Iizuka:
A high OIP3 quadrature mixer using cross-coupled transconductor. CICC 2005: 345-348 - 2002
- [j3]Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. IEEE J. Solid State Circuits 37(3): 349-356 (2002) - 2001
- [j2]Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz:
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. IEEE J. Solid State Circuits 36(3): 385-397 (2001) - [c3]Daniel Senderowicz, Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto:
Embedded anti-aliasing in switched-capacitor ladder filters. CICC 2001: 13-16 - 2000
- [c2]Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. CICC 2000: 35-38
1990 – 1999
- 1999
- [j1]Tetsuya Yagi, Seiji Kameda, Kunihiko Iizuka:
A parallel analog intelligent vision sensor with a variable receptive field. Syst. Comput. Jpn. 30(1): 60-69 (1999) - 1996
- [c1]Kunihiko Iizuka, Masayuki Miyamoto, Hirofumi Matsui:
Dynamically Adaptable CMOS Winner-Take-All Neural Network. NIPS 1996: 713-719
Coauthor Index
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