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Wen-Hung Huang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Wen-Hung Kevin Huang
(aka: Wen-Hung Huang 0001) — TU Dortmund, Germany
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2020 – today
- 2024
- [c7]Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee:
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. VLSI Technology and Circuits 2024: 1-2 - [i1]Chin-Hung Chen, Wen-Hung Huang, Boris Karanov, Alex Young, Yan Wu, Wim J. van Houtum:
Analysis of Impulsive Interference in Digital Audio Broadcasting Systems in Electric Vehicles. CoRR abs/2405.10828 (2024) - 2020
- [j4]Mu-Shan Lin
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020) - [c6]Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny:
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c5]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28- - [c4]Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh:
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. VLSI Circuits 2019: 272- - 2016
- [c3]Mu-Shan Lin, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y.-H. Chen, C.-C. Kuo, Shih-Peng Tai, Kazuyoshi Yamada:
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package. Hot Chips Symposium 2016: 1-32 - 2014
- [j3]Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta:
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. IEEE J. Solid State Circuits 49(4): 1063-1074 (2014) - 2010
- [c2]Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu:
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC 2010: 1-4
2000 – 2009
- 2009
- [j2]Rong-Fuh Day, Chien-Huang Lin, Wen-Hung Huang, Sheng-Hsiung Chuang:
Effects of music tempo and task difficulty on multi-attribute decision-making: An eye-tracking approach. Comput. Hum. Behav. 25(1): 130-143 (2009) - 2008
- [c1]Chin-Feng Lee, Pei-Yan Pai, Wen-Hung Huang, Chin-Chen Chang:
An Effective Demosaicking and Zooming Algorithm for CFA Images. IIH-MSP 2008: 1150-1153 - 2007
- [j1]Chin-Chen Chang, Yu-Chiang Li, Wen-Hung Huang:
TFRP: An efficient microaggregation algorithm for statistical disclosure control. J. Syst. Softw. 80(11): 1866-1878 (2007)
Coauthor Index
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