default search action
Srinivasan Murali
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
- [c46]Srinivasan Murali
, Wenqiang Jin
Continuous Authentication Using Human-Induced Electric Potential. ACSAC 2023: 409-423 - 2022
- [j19]Huadi Zhu, Tianhao Li, Chaowei Wang, Wenqiang Jin, Srinivasan Murali, Mingyan Xiao, Dongqing Ye, Ming Li
EyeQoE: A Novel QoE Assessment Model for 360-degree Videos Using Ocular Behaviors. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 6(1): 39:1-39:26 (2022) - 2021
- [j18]Wenqiang Jin, Srinivasan Murali, YoungTak Cho, Huadi Zhu, Tianhao Li, Rachael Thompson Panik, Anika Rimu, Shuchisnigdha Deb, Kari E. Watkins
CycleGuard: A Smartphone-based Assistive Tool for Cyclist Safety Using Acoustic Ranging. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 5(4): 163:1-163:30 (2021) - [c45]Wenqiang Jin, Srinivasan Murali, Huadi Zhu, Ming Li
Periscope: A Keystroke Inference Attack Using Human Coupled Electromagnetic Emanations. CCS 2021: 700-714 - 2020
- [j17]Huadi Zhu, Wenqiang Jin, Mingyan Xiao, Srinivasan Murali, Ming Li:
BlinKey: A Two-Factor User Authentication Method for Virtual Reality Devices. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 4(4): 164:1-164:29 (2020) - [c44]Wenqiang Jin, Ming Li
Harnessing the Ambient Radio Frequency Noise for Wearable Device Pairing. CCS 2020: 1135-1148 - [c43]Wenjun Jiang, Hongfei Xue
Towards 3D human pose construction using wifi. MobiCom 2020: 23:1-23:14
2010 – 2019
- 2018
- [j16]Grégoire Surrel
Online Obstructive Sleep Apnea Detection on Medical Wearable Sensors. IEEE Trans. Biomed. Circuits Syst. 12(4): 762-773 (2018) - 2016
- [j15]Alair Dias Junior, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Methods for reliable estimation of pulse transit time and blood pressure variations using smartphone sensors. Microprocess. Microsystems 46: 84-95 (2016) - [c42]Dionisije Sopic, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation. DATE 2016: 726-731 - [c41]Elisabetta De Giovanni
Ultra-Low Power Estimation of Heart Rate Under Physical Activity Using a Wearable Photoplethysmographic System. DSD 2016: 553-560 - [c40]Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza:
Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea. ISVLSI 2016: 230-235 - 2015
- [c39]Srinivasan Murali, Francisco J. Rincón, David Atienza:
A Wearable Device for Physical and Emotional Health Monitoring. CinC 2015: 121-124 - [c38]Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza:
Real-Time Probabilistic Heart-Beat Classification and Correction for Embedded Systems. CinC 2015: 161-164 - [c37]Alair Dias Junior, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone. DSD 2015: 173-180 - [c36]Manoj Padmanabhan, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Energy-aware embedded classifier design for real-time emotion analysis. EMBC 2015: 2275-2278 - [c35]Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza:
Design of ultra-low-power smart wearable systems. LATS 2015: 1-2 - 2014
- [c34]Rubén Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali:
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. DAC 2014: 17:1-17:6 - 2013
- [j14]Dara Rahmati
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip. IEEE Trans. Computers 62(3): 452-467 (2013) - [j13]Ciprian Seiculescu, Dara Rahmati
Designing best effort networks-on-chip to meet hard latency constraints. ACM Trans. Embed. Comput. Syst. 12(4): 108:1-108:23 (2013) - 2012
- [j12]Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electr. Comput. Eng. 2012: 537286:1-537286:12 (2012) - 2011
- [c33]Ciprian Seiculescu, Srinivasan Murali, Luca Benini
A DRAM Centric NoC Architecture and Topology Design Approach. ISVLSI 2011: 54-59 - [c32]M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini
A Method for Integrating Network-on-Chip Topologies with 3D ICs. ISVLSI 2011: 60-65 - [c31]Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli:
A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI 2011: 206-211 - [p2]Ciprian Seiculescu, Srinivasan Murali, Luca Benini
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. Low Power Networks-on-Chip 2011: 199-222 - [p1]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks. 3D Integration for NoC-based SoC Architectures 2011: 193-223 - 2010
- [j11]Ciprian Seiculescu, Srinivasan Murali, Luca Benini
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1987-2000 (2010) - [j10]Ciprian Seiculescu, Srinivasan Murali, Luca Benini
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 364-368 (2010) - [c30]Srinivasan Murali, Luca Benini
Design of networks on chips for 3D ICs. ASP-DAC 2010: 167-168 - [c29]Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini
Networks on Chips: from research to products. DAC 2010: 300-305 - [c28]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. DATE 2010: 1625-1628
2000 – 2009
- 2009
- [b1]Srinivasan Murali:
Designing Reliable and Efficient Networks on Chips. Lecture Notes in Electrical Engineering 34, Springer 2009, ISBN 978-1-4020-9756-0, pp. 1-189 [contents] - [j9]Almir Mutapcic, Stephen P. Boyd, Srinivasan Murali, David Atienza
Processor Speed Control With Thermal Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1994-2008 (2009) - [c27]Srinivasan Murali, Ciprian Seiculescu, Luca Benini
Synthesis of networks on chips for 3D systems on chips. ASP-DAC 2009: 242-247 - [c26]Vincenzo Rana
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. CODES+ISSS 2009: 325-334 - [c25]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
NoC topology synthesis for supporting shutdown of voltage islands in SoCs. DAC 2009: 822-825 - [c24]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. DATE 2009: 9-14 - [c23]Dara Rahmati
A method for calculating hard QoS guarantees for Networks-on-Chip. ICCAD 2009: 579-586 - [c22]Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC 2009: 379-382 - 2008
- [j8]David Atienza
Network-on-Chip design and synthesis outlook. Integr. 41(3): 340-359 (2008) - [c21]Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. DATE 2008: 110-115 - 2007
- [j7]Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini:
Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007) - [j6]Srinivasan Murali, Luca Benini
An Application-Specific Design Methodology for On-Chip Crossbar Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1283-1296 (2007) - [j5]Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini
Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1297-1310 (2007) - [j4]Srinivasan Murali, David Atienza
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 869-880 (2007) - [j3]Srinivasan Murali, David Atienza, Luca Benini
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees. VLSI Design 2007: 37627:1-37627:11 (2007) - [c20]Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli:
Temperature-aware processor frequency assignment for MPSoCs using convex optimization. CODES+ISSS 2007: 111-116 - [c19]Antonio Pullini, Federico Angiolini, Paolo Meloni
NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282 - [c18]Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza
Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64 - [i1]Srinivasan Murali, Giovanni De Micheli:
An Application-Specific Design Methodology for STbus Crossbar Generation. CoRR abs/0710.4671 (2007) - 2006
- [c17]Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
Mapping and configuration methods for multi-use-case networks on chips. ASP-DAC 2006: 146-151 - [c16]Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. CODES+ISSS 2006: 130-135 - [c15]Srinivasan Murali, David Atienza, Luca Benini
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. DAC 2006: 845-848 - [c14]Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli:
A methodology for mapping multiple use-cases onto networks on chips. DATE 2006: 118-123 - [c13]Srinivasan Murali, Paolo Meloni
Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362 - [c12]Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Reliability Support for On-Chip Memories Using Networks-on-Chip. ICCD 2006: 389-396 - [c11]Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. SoC 2006: 1-4 - [c10]Paolo Meloni
Routing Aware Switch Hardware Customization for Networks on Chips. Nano-Net 2006: 1-5 - [c9]Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163 - [c8]Srinivasan Murali, Paolo Meloni
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. VLSI-SoC (Selected Papers) 2006: 337-355 - 2005
- [j2]Srinivasan Murali, Theo Theocharides
Analysis of Error Recovery Schemes for Networks on Chips. IEEE Des. Test Comput. 22(5): 434-442 (2005) - [j1]Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Trans. Parallel Distributed Syst. 16(2): 113-129 (2005) - [c7]Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. ASP-DAC 2005: 27-32 - [c6]Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli:
Performance driven reliable link design for networks on chips. ASP-DAC 2005: 749-754 - [c5]Srinivasan Murali, Giovanni De Micheli
An Application-Specific Design Methodology for STbus Crossbar Generation. DATE 2005: 1176-1181 - [c4]Srinivasan Murali:
Design Methodologies and CAD Tool Flows for Networks on Chips. SoC 2005: 1 - 2004
- [c3]Srinivasan Murali, Giovanni De Micheli:
SUNMAP: a tool for automatic topology selection and generation for NoCs. DAC 2004: 914-919 - [c2]Antoine Jalabert, Srinivasan Murali, Luca Benini
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. DATE 2004: 884-889 - [c1]Srinivasan Murali, Giovanni De Micheli:
Bandwidth-Constrained Mapping of Cores onto NoC Architectures. DATE 2004: 896-903
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:17 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: