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Jianghua Wan
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2010 – 2019
- 2016
- [c9]Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang:
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. ISVLSI 2016: 426-430 - 2015
- [c8]Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch
, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen:
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. ISVLSI 2015: 398-403 - 2014
- [j8]Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning:
FT-Matrix: A Coordination-Aware Architecture for Signal Processing. IEEE Micro 34(6): 64-73 (2014) - 2013
- [j7]Kai Zhang, Shuming Chen, Yaohua Wang, Jianghua Wan:
Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors. IEICE Electron. Express 10(9): 20130147 (2013) - [j6]Hui Yang, Shuming Chen, Jianghua Wan, Huanyao Dai:
Decoupled iteration mapping: improving dependency-loop performance on SIMD processors. IEICE Electron. Express 10(21): 20130798 (2013) - [j5]Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu:
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. IEICE Trans. Inf. Syst. 96-D(2): 365-369 (2013) - [c7]Yaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang, Wei Liu, Xi Ning:
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments. HPCA 2013: 603-614 - [c6]Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang:
Redefining the relationship between scalar and parallel units in SIMD architectures. ISCAS 2013: 781-784 - [c5]Ting Chen, Hengzhu Liu, Jianghua Wan:
Real-Time Implementation of 4x4 MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor. NCCET 2013: 33-43 - 2012
- [j4]Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures. IEEE Comput. Archit. Lett. 11(2): 37-40 (2012) - [j3]Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning:
A cost conscious performance model for media processors. IEICE Electron. Express 9(11): 978-984 (2012) - [c4]Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen:
Architectural Implications for SIMD Processors in the Wireless Communication Domain. HPCC-ICESS 2012: 1199-1204 - 2011
- [j2]Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang:
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. IEICE Electron. Express 8(24): 2106-2111 (2011) - [c3]Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen:
Design and chip implementation of a heterogeneous multi-core DSP. ASP-DAC 2011: 91-92 - [c2]Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen:
AIFSP: An Adaptive Instruction Flow Stream Processor. ISVLSI 2011: 272-277 - [c1]Sheng Liu, Shuming Chen, Jianghua Wan, Haiyan Chen, Yaohua Wang:
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle. NAS 2011: 348-354 - 2010
- [j1]Shuming Chen, Jianghua Wan, Jianzhuang Lu, Zhong Liu, Hai-Yan Sun, Yong-Jie Sun, Hengzhu Liu, Xiang-Yuan Liu, Zhentao Li, Yi Xu, Xiaowen Chen:
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP. J. Comput. Sci. Technol. 25(2): 214-224 (2010)
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