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Josep M. Codina
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2010 – 2019
- 2015
- [j4]Enric Gibert, Raúl Martínez, Carlos Madriles, Josep M. Codina:
Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units. IEEE Comput. Archit. Lett. 14(1): 62-65 (2015) - 2012
- [j3]Abhishek Deb, Josep M. Codina, Antonio González
:
A HW/SW Co-designed Programmable Functional Unit. IEEE Comput. Archit. Lett. 11(1): 9-12 (2012) - 2011
- [c14]Abhishek Deb, Josep M. Codina, Antonio González:
A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. Interaction between Compilers and Computer Architectures 2011: 1-8 - [c13]Abhishek Deb, Josep M. Codina, Antonio González
SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. Conf. Computing Frontiers 2011: 1 - [c12]Abhishek Deb, Josep M. Codina, Antonio González
A Power-Efficient Co-designed Out-of-Order Processor. SBAC-PAD 2011: 1-8
2000 – 2009
- 2009
- [j2]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. IEEE Trans. Computers 58(6): 770-783 (2009) - [c11]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT 2009: 15-25 - [c10]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA 2009: 474-483 - 2008
- [c9]Qiong Cai, Josep M. Codina, José González, Antonio González
A software-hardware hybrid steering mechanism for clustered microarchitectures. IPDPS 2008: 1-12 - 2007
- [c8]Josep M. Codina, F. Jesús Sánchez, Antonio González
Virtual Cluster Scheduling Through the Scheduling Graph. CGO 2007: 89-101 - [c7]Alex Aletà, Josep M. Codina, Antonio González
Heterogeneous Clustered VLIW Microarchitectures. CGO 2007: 354-366 - 2005
- [c6]Alex Aletà, Josep M. Codina, Antonio González
Demystifying on-the-fly spill code. PLDI 2005: 180-189 - 2004
- [j1]Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1(2): 127-151 (2004) - 2003
- [c5]Alex Aletà, Josep M. Codina, Antonio González
Instruction Replication for Clustered Microarchitectures. MICRO 2003: 326-338 - 2002
- [c4]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. IEEE PACT 2002: 281-290 - [c3]Josep M. Codina, Josep Llosa, Antonio González:
A comparative study of modulo scheduling techniques. ICS 2002: 97-106 - 2001
- [c2]Josep M. Codina, F. Jesús Sánchez, Antonio González:
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. IEEE PACT 2001: 175-184 - [c1]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
Graph-partitioning based instruction scheduling for clustered processors. MICRO 2001: 150-159
Coauthor Index
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