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Yuyun Liao
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2010 – 2019
- 2019
- [j4]Pascal Andreas Meinerzhagen
, Carlos Tokunaga
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [j3]Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham N. Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios D. Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang:
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro 38(1): 82-99 (2018) - [c4]Pascal Meinerzhagen, Carlos Tokunaga
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40
2000 – 2009
- 2002
- [j2]Yuyun Liao, David B. Roberts:
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature. IEEE J. Solid State Circuits 37(7): 926-931 (2002) - 2001
- [j1]Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen J. Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch:
An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J. Solid State Circuits 36(11): 1599-1608 (2001)
1990 – 1999
- 1996
- [c3]Yuyun Liao, D. M. H. Walker:
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. ITC 1996: 767-775 - [c2]Yuyun Liao, Mi Lu, Nian-Feng Tzeng:
The Palindrome network for fault-tolerant interconnection. SPDP 1996: 556-561 - [c1]Yuyun Liao, D. M. H. Walker:
Optimal voltage testing for physically-based faults. VTS 1996: 344-353
Coauthor Index
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