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Takushi Hashida
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2010 – 2019
- 2018
- [c6]Alexander van Renen
, Viktor Leis, Alfons Kemper, Thomas Neumann, Takushi Hashida, Kazuichi Oe
Managing Non-Volatile Memory in Database Systems. SIGMOD Conference 2018: 1541-1555 - 2015
- [c5]Yoshifumi Ujibashi, Minoru Nakamura, Tsuguchika Tabaru, Takushi Hashida, Motoyuki Kawaba, Lilian Harada:
Design of a Shared Memory mechanism for efficient paralell processing in PostgreSQL. IISA 2015: 1-6 - 2014
- [c4]Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura:
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC 2014: 1-2 - 2013
- [j5]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits 48(12): 3258-3267 (2013) - [c3]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC 2013: 36-37 - 2011
- [j4]Takushi Hashida, Yuuki Araga
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Trans. Electron. 94-C(6): 1016-1023 (2011) - [j3]Takushi Hashida, Makoto Nagata
An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. IEEE J. Solid State Circuits 46(4): 789-796 (2011) - [c2]Takushi Hashida, Yuuki Araga, Makoto Nagata
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS 2011: 70-75 - 2010
- [j2]Takushi Hashida, Makoto Nagata
Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails. IEICE Trans. Electron. 93-C(6): 842-848 (2010) - [c1]Yuuki Araga, Takushi Hashida, Makoto Nagata
An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS 2010: 3557-3560
2000 – 2009
- 2007
- [j1]Koichiro Noguchi, Takushi Hashida, Makoto Nagata
On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. IEICE Trans. Electron. 90-C(6): 1189-1196 (2007)
Coauthor Index
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