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Jaushin Lee
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Books and Theses
- 1992
- [b1]Jaushin Lee:
Architectural Level Test Generation and Fault Simulation. University of Illinois Urbana-Champaign, USA, 1992
Journal Articles
- 1996
- [j4]Jaushin Lee, Janak H. Patel:
Hierarchical test generation under architectural level functional constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1144-1151 (1996) - 1994
- [j3]Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 920-934 (1994) - [j2]Jaushin Lee, Janak H. Patel:
Architectural level test generation for microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1288-1300 (1994) - 1993
- [j1]Jaushin Lee, Janak H. Patel:
An architectural level test generator based on nonlinear equation solving. J. Electron. Test. 4(2): 137-150 (1993)
Conference and Workshop Papers
- 1993
- [c9]Jaushin Lee, Janak H. Patel:
Testability analysis based on structural and behavioral information. VTS 1993: 139-146 - [c8]Jaushin Lee, Vivek Chickermane, Janak H. Patel:
Impact of high level functional constraints on testability. VTS 1993: 309-312 - 1992
- [c7]Jaushin Lee, Janak H. Patel:
Hierarchical Test Generation under Intensive Global Functional Constraints. DAC 1992: 261-266 - [c6]Vivek Chickermane, Jaushin Lee, Janak H. Patel:
A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD 1992: 620-624 - [c5]Jaushin Lee, Janak H. Patel:
An Instruction Sequence Assembling Methodology for Testing Microprocessors. ITC 1992: 49-58 - [c4]Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Design for Testability Using Architectural Descriptions. ITC 1992: 752-761 - 1991
- [c3]Jaushin Lee, Janak H. Patel:
An Architectural Level Test Generator for a Hierarchical Design Environment. FTCS 1991: 44-51 - [c2]Jaushin Lee, Janak H. Patel:
A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. ICCAD 1991: 458-461 - [c1]Jaushin Lee, Janak H. Patel:
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. ITC 1991: 729-738
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