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Giuseppe Ascia
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2020 – today
- 2024
- [c54]Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. DAC 2024: 236:1-236:6 - [c53]Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania:
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. ISCAS 2024: 1-5 - [c52]Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Hamaad Rafique:
Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. MOST 2024: 251-259 - [i5]Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania:
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. CoRR abs/2403.00766 (2024) - [i4]Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. CoRR abs/2404.08950 (2024) - [i3]Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. CoRR abs/2406.11452 (2024) - 2023
- [j26]Enrico Russo
, Maurizio Palesi
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. IEEE Internet Things J. 10(2): 1800-1812 (2023) - [c51]Enrico Russo
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. CF 2023: 134-143 - [i2]Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR abs/2306.15552 (2023) - [i1]Fabrizio Ferrandi
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR abs/2311.17815 (2023) - 2022
- [j25]Enrico Russo
DNN Model Compression for IoT Domain-Specific Hardware Accelerators. IEEE Internet Things J. 9(9): 6650-6662 (2022) - [c50]Enrico Russo, Maurizio Palesi, Salvatore Monteleone
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. DATE 2022: 226-231 - [c49]Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. IPDPS Workshops 2022: 16-23 - [c48]Enrico Russo, Maurizio Palesi, Salvatore Monteleone
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. MECO 2022: 1-4 - 2021
- [c47]Enrico Russo, Maurizio Palesi, Salvatore Monteleone
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. PerCom Workshops 2021: 161-166 - 2020
- [j24]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone
Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 16(2): 21:1-21:27 (2020) - [c46]Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. DSD 2020: 526-533 - [c45]Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops 2020: 54-63 - [c44]Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. NOCS 2020: 1-6
2010 – 2019
- 2019
- [c43]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS 2019: 227-234 - [c42]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone
Analyzing networks-on-chip based deep neural networks. NOCS 2019: 23:1-23:2 - 2018
- [c41]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone
Approximate Wireless Networks-on-Chip. DCIS 2018: 1-6 - [c40]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone
Improving energy consumption of NoC based architectures through approximate communication. MECO 2018: 1-4 - 2016
- [j23]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Exploiting antenna directivity in wireless NoC architectures. Microprocess. Microsystems 43: 59-66 (2016) - [j22]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania:
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1769-1782 (2016) - [j21]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1535-1545 (2016) - [c39]Giuseppe Ascia, Vincenzo Catania, Raffaele Di Natale
Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection. WETICE 2016: 205-210 - 2015
- [j20]Maurizio Palesi, Davide Patti
Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. J. Comput. Sci. 11(3): 552-566 (2015) - [c38]Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono:
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. DATE 2015: 513-518 - 2014
- [c37]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. DATE 2014: 1-6 - [c36]Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
A Closed Loop Control based Power Manager for WiNoC Architectures. MES 2014: 60-63 - 2013
- [j19]Alessandro G. Di Nuovo
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers. J. Intell. Fuzzy Syst. 25(2): 493-504 (2013) - [c35]Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania:
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. DSD 2013: 505-512 - [c34]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. DSD 2013: 941-944 - [c33]Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. HPCC/EUC 2013: 2088-2095 - [c32]Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
NoC links energy reduction through link voltage scaling. ICSAMOS 2013: 113-120 - 2012
- [c31]Alessandro G. Di Nuovo
A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems. PPSN (2) 2012: 102-111 - 2011
- [j18]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11(1): 382-398 (2011) - [j17]Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania:
Data Encoding Schemes in Networks on Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 774-786 (2011)
2000 – 2009
- 2009
- [c30]Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania:
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD 2009: 119-126 - 2008
- [j16]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008) - 2007
- [j15]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo
Efficient design space exploration for application specific systems-on-a-chip. J. Syst. Archit. 53(10): 733-750 (2007) - 2006
- [j14]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. Univers. Comput. Sci. 12(4): 370-394 (2006) - [j13]Giuseppe Ascia, Vincenzo Catania, Daniela Panno:
An integrated fuzzy-GA approach for buffer management. IEEE Trans. Fuzzy Syst. 14(4): 528-541 (2006) - [c29]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation 2006: 1736-1743 - [c28]Alessandro G. Di Nuovo
Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228 - [c27]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTIMedia 2006: 79-84 - [c26]Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122 - 2005
- [j12]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 635-645 (2005) - [j11]Giuseppe Ascia, Vincenzo Catania, Daniela Panno:
An evolutionary management scheme in high-performance packet switches. IEEE/ACM Trans. Netw. 13(2): 262-275 (2005) - [c25]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91 - [c24]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943 - [c23]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119 - [c22]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093 - 2004
- [j10]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evol. Comput. 8(4): 329-346 (2004) - [c21]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187 - [c20]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198 - 2003
- [c19]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato:
An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation 2003: 107-114 - [c18]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTIMedia 2003: 65-72 - [c17]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato:
An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81 - [c16]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30 - [c15]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431 - 2002
- [c14]Giuseppe Ascia, Vincenzo Catania, Daniela Panno:
An efficient buffer management policy based on an integrated Fuzzy-GA approach. INFOCOM 2002: 1042-1048 - [c13]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Framework for Design Space Exploration of Parameterized VLSI Systems. ASP-DAC/VLSI Design 2002: 245-250 - 2001
- [j9]Giuseppe Ascia, Vincenzo Catania, Daniela Panno:
An efficient fuzzy system for traffic management in high-speed packet-switched networks. Soft Comput. 5(4): 247-256 (2001) - [j8]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
An Instruction-Level Power Analysis Model with Data Dependency. VLSI Design 12(2): 245-273 (2001) - [c12]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
Parameterised system design based on genetic algorithms. CODES 2001: 177-182 - [c11]Giuseppe Ascia, Vincenzo Catania:
A General Purpose Processor Oriented Fuzzy Reasoning. FUZZ-IEEE 2001: 352-355 - [c10]Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168 - [c9]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno:
A Fuzzy Buffer Management Scheme For ATM and IP Networks. INFOCOM 2001: 1539-1547 - [c8]Giuseppe Ascia, Vincenzo Catania, Daniela Panno:
An adaptive fuzzy threshold scheme for high performance shared-memory switches. SAC 2001: 456-461 - 2000
- [c7]Giuseppe Ascia, Vincenzo Catania:
A pipeline parallel architecture for a fuzzy inference processor. FUZZ-IEEE 2000: 257-262
1990 – 1999
- 1999
- [j7]Giuseppe Ascia, Vincenzo Catania, Marco Russo
VLSI hardware architecture for complex fuzzy systems. IEEE Trans. Fuzzy Syst. 7(5): 553-570 (1999) - [c6]Giuseppe Ascia, Vincenzo Catania:
An Optimized Parallel RISC Processor for Fuzzy Computing. Applied Informatics 1999: 454-456 - 1998
- [c5]Giuseppe Ascia, Vincenzo Catania:
A Framework for a Parallel Architecture Dedicated to Soft Computing. VLSI Design 1998: 318-321 - 1997
- [j6]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno:
A VLSI fuzzy expert system for real-time traffic control in ATM networks. IEEE Trans. Fuzzy Syst. 5(1): 20-31 (1997) - [c4]Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili:
Design of a VLSI Hardware PET Decoder. VLSI Design 1997: 253-256 - 1996
- [j5]Giuseppe Ascia, Vincenzo Catania:
An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning. Int. J. Artif. Intell. Tools 5(1-2): 41-60 (1996) - [j4]Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita:
A Reconfigurable Parallel Architecture for a Fuzzy Processor. Inf. Sci. 88(1-4): 299-315 (1996) - 1995
- [j3]Vincenzo Catania, Giuseppe Ascia:
A VLSI Parallel Architecture for Fuzzy Expert Systems. Int. J. Pattern Recognit. Artif. Intell. 9(2): 421-447 (1995) - [j2]Abraham Kandel, Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita, Andrés Jaramillo-Botero, Yoichi Miyake, Hua Harry Li, Nowell Godfrey, Yuandong Ji, Shuwei Guo, Liliane Peters, Krishna Rao Valavala, Mahmoud A. Manzoul, Antonio Ruiz, Julio Gutiérrez, Felipe Fernández:
Fuzzy Hardware Challenges. IEEE Micro 15(6): 61-67 (1995) - [j1]Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo
Designing for parallel fuzzy computing. IEEE Micro 15(6): W1-W11 (1995) - [c3]Giuseppe Ascia, Vincenzo Catania:
An efficient hardware architecture to support complex fuzzy reasoning. ICTAI 1995: 250-257 - [c2]Giuseppe Ascia, Giuseppe Ficili, Daniela Panno:
Design of a VLSI fuzzy processor for ATM traffic sources management. LCN 1995: 62-71 - [c1]Giuseppe Ascia, Vincenzo Catania:
Design of a VLSI parallel processor for fuzzy computing. VLSI Design 1995: 315-320
Coauthor Index
[c54] [c53] [i5] [i4] [i3] [j26] [c51] [j25] [c50] [c49] [c48] [c47] [j24] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [j23] [j22] [j21] [c39] [j20] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [j18] [j17] [c30] [j16] [j15] [j14] [j13] [c29] [c28] [c27] [c26] [j12] [j11] [c25] [c24] [c23] [c22] [j10] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j9] [j8] [c12] [c11] [c10] [c9] [c8] [c7] [j7] [c6] [c5] [j6] [c4] [j5] [j4] [j3] [j2] [j1] [c3] [c1]
[c54] [c53] [c52] [i5] [i4] [i3] [j26] [c51] [i2] [i1] [j25] [c50] [c49] [c48] [c47] [j24] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [j23] [j22] [j21] [j20] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [j18] [j17] [c30] [j16] [j15] [j14] [c29] [c28] [c27] [c26] [j12] [c25] [c24] [c23] [c22] [j10] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c13] [j8] [c12] [c10]
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