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Qiaochu Zhang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Frank Zhang 0001 (aka: Qiaochu Zhang 0001) — Facebook AI, USA
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2020 – today
- 2024
- [j2]Qiaochu Zhang
, Hsiang-Chun Cheng
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits 59(1): 40-51 (2024) - [c16]Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta:
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE 2024: 1-2 - [c15]Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen:
Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c14]Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen:
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c13]Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC 2023: 1-2 - [c12]Shiyu Su, Qiaochu Zhang
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC 2023: 1-2 - [c11]Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC 2023: 213-216 - [c10]Qiaochu Zhang
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC 2023: 226-227 - 2022
- [j1]Qiaochu Zhang
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57(1): 80-89 (2022) - [c9]Shiyu Su, Qiaochu Zhang
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC 2022: 100-107 - [c8]Shiyu Su, Qiaochu Zhang
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC 2022: 526-531 - [c7]Qiaochu Zhang
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC 2022: 1021-1026 - 2021
- [c6]Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC 2021: 505-510 - [c5]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c4]Qiaochu Zhang
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC 2021: 410-412 - [i2]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR abs/2112.07824 (2021) - [i1]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR abs/2112.07825 (2021) - 2020
- [c3]Qiaochu Zhang
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD 2020: 118:1-118:9 - [c2]Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD 2020: 119:1-119:9
2010 – 2019
- 2019
- [c1]Shuxiu Cai, Xiaxia Yu, Qiaochu Zhang, Chuan Huang
Is hippocampus getting bumpier with age: a quantitative analysis of fine-scale dentational feature under the hippocampus on 552 healthy subjects. Image Processing 2019: 1094935
Coauthor Index
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