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Hiromasa Takahashi
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2020 – today
- 2023
- [c5]Kazuhito Ogawa, Yusuke Osaki, Tetsuya Kawamura, Hiromasa Takahashi, Satoshi Taguchi, Yoichiro Fujii, Kengo Kurosaka, Kohei Iyori, Naoki Watanabe:
Conducting an Experiment at Multiple Sites with Small Subject Pools: How is Raven Score Effective as a Covariate? IEEE Big Data 2023: 3202-3211 - 2022
- [j8]Toan Luu Duc Huynh
, Marc Oliver Rieger, Mei Wang
Cheating, Trust and Social Norms: Data from Germany, Vietnam, China, Taiwan, and Japan. Data 7(10): 137 (2022) - 2020
- [j7]Hiromasa Takahashi
Can players avoid the tragedy of the commons in a joint debt game? Int. J. Game Theory 49(4): 975-1002 (2020)
2010 – 2019
- 2011
- [c4]Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Makiko Ito, Yoshio Hirose, Hiromasa Takahashi:
A vector coprocessor architecture for embedded systems. ISOCC 2011: 195-198 - 2010
- [j6]Riichiro Takemura, Takayuki Kawahara
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45(4): 869-879 (2010)
2000 – 2009
- 2008
- [j5]Takayuki Kawahara
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits 43(1): 109-120 (2008) - 2007
- [c3]Takayuki Kawahara
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS 2007: 1011-1014 - [c2]Takayuki Kawahara
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC 2007: 480-617 - 2004
- [j4]Hiromasa Takahashi, Hiroaki Nishi
Autonomous decentralized control for formation of multiple mobile robots considering ability of robot. IEEE Trans. Ind. Electron. 51(6): 1272-1279 (2004)
1990 – 1999
- 1999
- [j3]Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada:
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. IEEE J. Solid State Circuits 34(11): 1619-1626 (1999) - 1998
- [j2]Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai:
A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. IEEE J. Solid State Circuits 33(11): 1640-1648 (1998) - 1993
- [j1]Makoto Awaga, Hiromasa Takahashi:
The μVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation. IEEE Micro 13(5): 24-36 (1993) - 1990
- [c1]Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto:
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. ICCD 1990: 347-350
Coauthor Index
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