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Sung-Gi Ahn
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2020 – today
- 2023
- [j3]Yesin Ryu
, Sung-Gi Ahn, Jaehoon Lee, Jaewon Park, Yong-Ki Kim
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. IEEE J. Solid State Circuits 58(4): 1051-1061 (2023) - 2022
- [c3]Yesin Ryu, Young-Cheon Kwon, Jaehoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je-Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Sukhan Lee, Kyounghwan Lim, Tae-Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, Hyoungmin Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. VLSI Technology and Circuits 2022: 130-131 - 2021
- [j2]Ki Chul Chun
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. IEEE J. Solid State Circuits 56(1): 199-211 (2021)
2010 – 2019
- 2019
- [j1]Cheol Kim
Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 605-615 (2019) - 2018
- [c2]Cheol Kim, Rak-Joo Sung, Sung-Gi Ahn, Jisu Min, Kee-Won Kwon:
Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line. ISCAS 2018: 1-4 - 2017
- [c1]Sung-Gi Ahn, Kee-Won Kwon:
Local NOR and global NAND match-line architecture for high performance CAM. MWSCAS 2017: 707-710
Coauthor Index
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