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Jingchang Bian
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2020 – today
- 2024
- [j9]Jingchang Bian
, Zhengfeng Huang, Yankun Lin, Zhao Yang, Huaguo Liang, Tianming Ni:
Reliability analysis and comparison of ring-PUF based on probabilistic models. Microelectron. J. 144: 106072 (2024) - [j8]Zhengfeng Huang, Peng Ye
A lightweight reversible multi-mode physical unclonable function. Microelectron. J. 154: 106469 (2024) - [j7]Zhengfeng Huang
Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 71-84 (2024) - [j6]Jingchang Bian
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations. ACM Trans. Design Autom. Electr. Syst. 29(1): 5:1-5:16 (2024) - [j5]Qingsong Peng
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. ACM Trans. Design Autom. Electr. Syst. 29(1): 13:1-13:17 (2024) - [c3]Jingchang Bian, Zhengfeng Huang, Ruixiang Liu, Yankun Lin, Zhao Yang, Huaguo Liang, Aibin Yan:
A RO-Integrated-LFSR-Based Nonlinear Strong PUF with Intrinsic Modeling Attacks Resilience. ITC-Asia 2024: 1-6 - [c2]Zhengfeng Huang, Yankun Lin, Fansheng Zeng, Jingchang Bian, Zhao Yang, Huaguo Liang, Yingchun Lu, Liang Yao, Xiaoqing Wen, Tianming Ni:
PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks. ITC-Asia 2024: 1-6 - 2023
- [j4]Tianming Ni
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5074-5085 (2023) - 2022
- [j3]Tianming Ni
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement. IEEE Des. Test 39(5): 34-42 (2022) - [c1]Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Xiaoqing Wen:
MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator. AsianHOST 2022: 1-6
2010 – 2019
- 2019
- [j2]Maoxiang Yi
A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 755-766 (2019) - 2017
- [j1]Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen:
Vernier ring based pre-bond through silicon vias test in 3D ICs. IEICE Electron. Express 14(18): 20170590 (2017)
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