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Hyung-Jong Ko
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2010 – 2019
- 2019
- [j2]Kyoung-Jun Moon
, Dong-Shin Jo
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. IEEE J. Solid State Circuits 54(9): 2532-2542 (2019) - 2018
- [j1]Il-Hoon Jang
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits 53(4): 1139-1148 (2018) - [c2]Kyung-Hoon Lee, Sang-Pil Nam, Jung-Ho Lee, Michael Choi, Hyung-Jong Ko, San-Ho Byun, Jin-chul Lee, Yong-Hoon Lee, Yeong-Cheol Rhee, Yoon-Kyung Choi, Byunghoon Kang, Changbyung Park, Sungsoo Park, Taesung Kim:
A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses. ISSCC 2018: 184-186
2000 – 2009
- 2001
- [c1]Robert M. Fox, Hyung-Jong Ko, William R. Eisenstadt
High-gain common-mode feedback circuits for differential log-domain filters. ISCAS (1) 2001: 560-563
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