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Zhizhong Zhang 0004
Person information
- affiliation: Beihang University, School of Microelectronics, Fert Beijing Research Institute, Center for Big Data and Brain Computing (BDBC), Beijing, China
Other persons with the same name
- Zhizhong Zhang (aka: ZhiZhong Zhang) — disambiguation page
- Zhizhong Zhang 0001
— East China Normal University, School of Computer Science and Technology, Shanghai, China (and 2 more)
- Zhizhong Zhang 0002
- Zhizhong Zhang 0003
- Zhizhong Zhang 0005
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2020 – today
- 2021
- [j5]Yue Zhang
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1193-1205 (2021) - 2020
- [j4]Jiang Nan, Kun Zhang
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic. IEEE Access 8: 87584-87591 (2020) - [j3]Jinkai Wang, Chenyu Lian, Yining Bai
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. 67-I(12): 4247-4258 (2020) - [c5]Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao:
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device. ACM Great Lakes Symposium on VLSI 2020: 259-264 - [c4]Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao:
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM. ACM Great Lakes Symposium on VLSI 2020: 351-356
2010 – 2019
- 2019
- [j2]Guanda Wang
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 215-225 (2019) - [c3]Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao:
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction. NANOARCH 2019: 1-6 - 2017
- [c2]Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao:
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction. NANOARCH 2017: 49-54 - 2016
- [j1]Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 629-638 (2016) - [c1]Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao:
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy. NANOARCH 2016: 141-142
Coauthor Index
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