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Soyeong Shin
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2020 – today
- 2022
- [j6]Soyeong Shin
, Yongjae Lee
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 814-818 (2022) - [j5]Jung-Woo Sull
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 874-878 (2022) - [j4]Woonghee Lee
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2056-2060 (2022) - [c5]Yunhee Lee
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits 2022: 30-31 - 2021
- [j3]Min-Seong Choo
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - 2020
- [j2]Sangyoon Lee
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j1]Soyeong Shin
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - [c4]Han-Gon Ko, Soyeong Shin
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC 2020: 128-130 - [c3]Soyeong Shin
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ISSCC 2020: 340-342
2010 – 2019
- 2019
- [c2]Han-Gon Ko, Soyeong Shin
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - 2017
- [c1]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495
Coauthor Index
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