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Nicolas Butzen
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2020 – today
- 2024
- [j6]Nicolas Butzen, Harish K. Krishnamurthy, Jingshu Yu, Khondker Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, James Waldemer, Christopher Pelto, James W. Tschanz:
A Monolithic 12.7 W/mm2, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology. IEEE J. Solid State Circuits 59(12): 4114-4123 (2024) - [c14]Nicolas Butzen, Harish Krishnamurthy, Jingshu Yu, Khondker Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, James Waldemer, Chris Pelto, James W. Tschanz:
28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter. ISSCC 2024: 462-464 - [c13]Jingshu Yu, Xiaosen Liu, Minxiang Gong, Nicolas Butzen, Sheldon Weng, Harish K. Krishnamurthy, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, Waldemer Jim, Christopher Pelto, James W. Tschanz, Vivek De:
A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c12]Nicolas Butzen, Harish Krishnamurthy, Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Michael Zelikson, James W. Tschanz, Jonathan Douglas:
A Monolithic 26A/mm2Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter. ISSCC 2023: 232-233 - 2022
- [j5]Nachiket V. Desai, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors. IEEE J. Solid State Circuits 57(4): 1090-1099 (2022) - [c11]Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De:
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. ISSCC 2022: 478-480 - 2021
- [c10]Nachiket V. Desai, Harish K. Krishnamurthy, William J. Lambert, Jingshu Yu, Han Wui Then, Nicolas Butzen, Sheldon Weng, Christopher Schaef, N. Nidhi, Marko Radosavljevic, Johann Rode, Justin Sandford, Kaladhar Radhakrishnan, Krishnan Ravichandran, Bernhard Sell, James W. Tschanz, Vivek De:
A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors. VLSI Circuits 2021: 1-2 - 2020
- [c9]Harish K. Krishnamurthy, Khondker Zakir Ahmed, Xiaosen Liu, Nachiket V. Desai, Suhwan Kim, Nicolas Butzen, Sally Amin, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Digital Control of Switching and Linear Integrated Voltage Regulators. CICC 2020: 1-4
2010 – 2019
- 2019
- [j4]Nicolas Butzen, Michiel Steyaert:
Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC-DC Converters. IEEE J. Solid State Circuits 54(4): 1039-1047 (2019) - [c8]Nicolas Butzen, Michiel Steyaert:
Advanced Multiphasing: Pushing the Envelope of Fully Integrated Power Conversion. CICC 2019: 1-8 - 2018
- [c7]Tim Thielemans, Nicolas Butzen, Athanasios Sarafianos, Michiel Steyaert, Filip Tavernier:
A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS. CICC 2018: 1-4 - [c6]Nicolas Butzen, Michiel Steyaert:
A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-Efficiency. VLSI Circuits 2018: 103-104 - 2017
- [j3]Nicolas Butzen, Michiel S. J. Steyaert:
MIMO Switched-Capacitor DC-DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution. IEEE J. Solid State Circuits 52(7): 1814-1824 (2017) - [j2]Nicolas Butzen, Michel S. J. Steyaert:
Design of Soft-Charging Switched-Capacitor DC-DC Converters Using Stage Outphasing and Multiphase Soft-Charging. IEEE J. Solid State Circuits 52(12): 3132-3141 (2017) - [c5]Michiel Steyaert, Athanasios Sarafianos, Nicolas Butzen, Elly De Pelecijn:
Fully integrated power management: The missing link? ECCTD 2017: 1-4 - [c4]Nicolas Butzen, Michiel Steyaert:
10.1 A 1.1W/mm2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging. ISSCC 2017: 178-179 - 2016
- [j1]Nicolas Butzen, Michiel S. J. Steyaert:
Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC-DC Converters. IEEE J. Solid State Circuits 51(12): 2843-2853 (2016) - [c3]Nicolas Butzen, Michiel Steyaert:
MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution. ESSCIRC 2016: 445-448 - [c2]Nicolas Butzen, Michiel Steyaert:
12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution. ISSCC 2016: 220-221 - 2015
- [c1]Michiel Steyaert, Filip Tavernier, Hans Meyvaert, Athanasios Sarafianos, Nicolas Butzen:
When hardware is free, power is expensive! Is integrated power management the solution? ESSCIRC 2015: 26-34
Coauthor Index
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last updated on 2024-12-17 20:59 CET by the dblp team
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