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Guilherme Paim
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2020 – today
- 2024
- [j27]Morgana M. A. da Rosa
, Guilherme Paim, Eduardo A. C. da Costa, Rafael Soares, Sergio Bampi:
AxRSU-2m: Higher-Order m-Bit Approximate Encoders for Radix-2m Squarer Units. Circuits Syst. Signal Process. 43(6): 3649-3678 (2024) - [j26]Roger Morales-Monge
Improving Netlist Transformation-Based Approximate Logic Synthesis Through Resynthesis. IEEE Embed. Syst. Lett. 16(3): 279-282 (2024) - [j25]Yuri Arbeletche, Guilherme Paim
MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4748-4752 (2024) - [j24]Léo Ribeiro, Patrícia U. L. da Costa, Guilherme Paim
VLSI Architecture for Energy-Efficient and Accurate Pre-Processing Pan-Tompkins Design. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4768-4772 (2024) - [c53]Jonas Crols, Guilherme Paim, Shirui Zhao, Marian Verhelst:
TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware. DATE 2024: 1-6 - 2023
- [j23]Morgana M. A. da Rosa
Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic. Circuits Syst. Signal Process. 42(2): 828-852 (2023) - [j22]Brunno Alves de Abreu
Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 86-95 (2023) - [j21]Pedro Tauã Lopes Pereira
ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 327-339 (2023) - [j20]Gerson D. Andrade, Matheus Silva
Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1264-1268 (2023) - [j19]Morgana Macedo Azevedo da Rosa
AxPPA: Approximate Parallel Prefix Adders. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 17-28 (2023) - [c52]Pedro Tauã Lopes Pereira, Guilherme Paim, Paulo F. Flores
AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation. DSN-W 2023: 183-186 - [c51]Morgana M. A. da Rosa
An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units. LASCAS 2023: 1-4 - [c50]Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Paulo F. Flores
Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design. NEWCAS 2023: 1-5 - 2022
- [j18]Bianca Silveira, Guilherme Paim
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. Circuits Syst. Signal Process. 41(3): 1577-1595 (2022) - [j17]Guilherme Paim
A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers. IEEE Trans. Computers 71(2): 349-363 (2022) - [j16]Brunno Alves Abreu
C2PAx: Complexity-Aware Constant Parameter Approximation for Energy-Efficient Tree-Based Machine Learning Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2683-2693 (2022) - [j15]Pedro Tauã Lopes Pereira
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4524-4534 (2022) - [j14]Guilherme Paim
Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop. IEEE Trans. Circuits Syst. Video Technol. 32(1): 398-410 (2022) - [c49]Tim Bücher
AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. ICCAD 2022: 152:1-152:9 - [c48]Patrícia U. L. da Costa, Morgana M. A. da Rosa, Guilherme Paim, Eduardo Antonio Cesar da Costa, Rafael Soares, Sergio Bampi:
An Efficient Exponential Unit Designed in VLSI CMOS with Custom Operators. ICECS 2022 2022: 1-4 - [c47]Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Sergio Bampi:
Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design. ICECS 2022 2022: 1-4 - [c46]Morgana Macedo Azevedo da Rosa, Guilherme Paim, Rafael Soares, Eduardo A. C. da Costa, Sergio Bampi:
Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking. ICECS 2022 2022: 1-4 - [c45]Morgana Macedo Azevedo da Rosa, Guilherme Paim, Jorge Castro-Godínez, Eduardo A. C. da Costa, Rafael Iankowski Soares, Sergio Bampi:
AxRSU: Approximate Radix-4 Squarer Unit. ISCAS 2022: 1655-1659 - [c44]Brunno A. Abreu, Guilherme Paim, Jorge Castro-Godínez, Mateus Grellert
On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators. LASCAS 2022: 1-4 - [c43]Patrícia U. L. da Costa, Pedro Tauã Lopes Pereira, Brunno A. Abreu, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi:
Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design. LASCAS 2022: 1-4 - [i1]Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch:
AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks. CoRR abs/2208.10868 (2022) - 2021
- [j13]Andrei La Rosa
Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals. Circuits Syst. Signal Process. 40(7): 3305-3337 (2021) - [j12]Guilherme da Costa Ferreira
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors. IET Comput. Digit. Tech. 15(3): 230-240 (2021) - [j11]Patrícia Ücker Leleu da Costa
Fixed-Point NLMS and IPNLMS VLSI Architectures for Accurate FECG and FHR Processing. IEEE Trans. Biomed. Circuits Syst. 15(5): 898-911 (2021) - [j10]Guilherme Paim
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1481-1492 (2021) - [j9]Henrique Seidel
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1814-1826 (2021) - [j8]Morgana Macedo Azevedo da Rosa
An Energy-Efficient Haar Wavelet Transform Architecture for Respiratory Signal Processing. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 597-601 (2021) - [j7]Pedro Tauã Lopes Pereira
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1402-1415 (2021) - [c42]Leandro Mateus Giacomini Rocha
LSTM-only Model for Low-complexity HR Estimation from Wrist PPG. EMBC 2021: 1068-1071 - [c41]Patrícia U. L. da Costa
Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations. ICECS 2021: 1-4 - [c40]Guilherme da Costa Ferreira
A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders. LASCAS 2021: 1-4 - [c39]Pedro Tauã Lopes Pereira
Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures. LASCAS 2021: 1-4 - 2020
- [j6]Vagner Guidotti, Guilherme Paim
Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling. Circuits Syst. Signal Process. 39(11): 5729-5757 (2020) - [j5]Guilherme Paim
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding. J. Real Time Image Process. 17(5): 1735-1754 (2020) - [j4]Guilherme Paim
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders. IEEE Trans. Circuits Syst. Video Technol. 30(10): 3814-3828 (2020) - [c38]Patrícia U. L. da Costa
An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing. ICECS 2020: 1-4 - [c37]Morgana M. A. da Rosa, Guilherme Paim
The Radix-2m Squared Multiplier. ICECS 2020: 1-4 - [c36]Morgana M. A. da Rosa, Guilherme Paim
Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design. ICECS 2020: 1-4 - [c35]Andrei La Rosa
Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination. ICECS 2020: 1-4 - [c34]Thomas V. Fontanari, Guilherme Paim
An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay. LASCAS 2020: 1-4 - [c33]Henrique Seidel, Morgana Macedo Azevedo da Rosa, Guilherme Paim
Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes. LASCAS 2020: 1-4 - [c32]Patrícia Ücker
Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design. LASCAS 2020: 1-4 - [c31]Mateus Terribele Leme, Guilherme Paim
Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture. MWSCAS 2020: 1084-1087 - [c30]Leandro M. G. Rocha
Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers. NEWCAS 2020: 182-185
2010 – 2019
- 2019
- [j3]Wagner Penny
High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator. J. Real Time Image Process. 16(1): 175-192 (2019) - [j2]Guilherme Paim
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 680-693 (2019) - [c29]Pedro Tauã Lopes Pereira
Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization. ICECS 2019: 650-653 - [c28]Vitor G. Lima, Guilherme Paim
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. ISCAS 2019: 1-5 - [c27]Rafael S. Ferreira, Guilherme Paim
HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. MWSCAS 2019: 331-334 - [c26]Brunno Abreu
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation. NEWCAS 2019: 1-4 - [c25]Guilherme Paim
Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors. NEWCAS 2019: 1-4 - 2018
- [c24]Luis F. Sequeira, Gustavo M. Santana
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors. NEWCAS 2018: 309-312 - [c23]Miguel R. Weirich, Guilherme Paim
A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series. NGCAS 2018: 53-56 - [c22]Brunno Abreu
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation. SBCCI 2018: 1-6 - 2017
- [j1]Bianca Silveira, Guilherme Paim
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3126-3137 (2017) - [c21]Leandro M. G. Rocha
Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers. ICECS 2017: 478-481 - [c20]Guilherme Paim
Improved goldschmidt algorithm for fast and energy-efficient fixed-point divider. ICECS 2017: 482-485 - [c19]Gustavo M. Santana
Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors. ICECS 2017: 486-489 - [c18]Bianca Silveira, Brunno Abreu, Guilherme Paim
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding. ICECS 2017: 490-493 - [c17]Brunno Abreu, Guilherme Paim
Exploiting absolute arithmetic for power-efficient sum of absolute differences. ICECS 2017: 522-525 - [c16]Leandro M. G. Rocha
Physical implementation of an ASIC-oriented SRAM-based viterbi decoder. ICECS 2017: 526-529 - [c15]Guilherme Paim
Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform. NEWCAS 2017: 25-28 - [c14]Bianca Silveira, Rafael S. Ferreira, Guilherme Paim
Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors. NEWCAS 2017: 277-280 - [c13]Raphael Dornelles, Guilherme Paim
A power-efficient 4-2 Adder Compressor topology. NEWCAS 2017: 281-284 - [c12]Guilherme Paim
A power-predictive environment for fast and power-aware ASIC-based FIR filter design. SBCCI 2017: 168-173 - 2016
- [c11]Guilherme Paim
A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing. ICECS 2016: 261-264 - [c10]Bianca Silveira, Guilherme Paim
Power-efficient sum of absolute differences architecture using adder compressors. ICECS 2016: 340-343 - [c9]Guilherme Paim
High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards. ICIP 2016: 2162-2166 - [c8]Guilherme Paim
An efficient sub-sample interpolator hardware for VP9-10 standards. ICIP 2016: 2167-2171 - [c7]Jones Goebel, Guilherme Paim
An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs. ISCAS 2016: 2202-2205 - [c6]Tiago Schiavon, Guilherme Paim
Exploiting adder compressors for power-efficient 2-D approximate DCT realization. LASCAS 2016: 383-386 - [c5]Guilherme Paim
Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform. NEWCAS 2016: 1-4 - 2015
- [c4]Guilherme Paim
Power efficient 2-D rounded cosine transform with adder compressors for image compression. ICECS 2015: 348-351 - [c3]Henrique Maich, Guilherme Paim
A multi-standard interpolation hardware solution for H.264 and HEVC. ICIP 2015: 2910-2914 - [c2]Henrique Maich, Guilherme Paim
A multi-standard interpolation filter for motion compensated prediction on high definition videos. LASCAS 2015: 1-4 - [c1]Wagner Penny
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos. SBCCI 2015: 12:1-12:6
Coauthor Index
[j27] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [c52] [c51] [c50] [j18] [j17] [j16] [j15] [j14] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [i1] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [c42] [c41] [c40] [c39] [j6] [j5] [j4] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j2] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j1] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c13] [c12] [c11]
Eduardo A. C. da Costa
aka: Eduardo Antonio Cesar da Costa
aka: Eduardo Antônio César da Costa
aka: Eduardo Costa 0001
aka: Eduardo Antonio Cesar da Costa
aka: Eduardo Antônio César da Costa
aka: Eduardo Costa 0001
[j27] [j25] [j24] [j23] [j21] [j20] [j19] [c52] [c51] [c50] [j18] [j17] [j15] [j14] [c48] [c47] [c46] [c45] [c43] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [c41] [c40] [c39] [j6] [j5] [j4] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j2] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j1] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c6] [c5] [c4]
Leandro M. G. Rocha
aka: Leandro Mateus Giacomini Rocha
aka: Leandro Mateus Giacomini Rocha
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last updated on 2024-12-02 21:28 CET by the dblp team
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