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Andrea Mondelli
Person information
- affiliation: Huawei Technologies Co., Ltd.
- affiliation (former): IRISA/INRIA, Rennes, France
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2020 – today
- 2023
- [j5]Biagio Peccerillo
, Elham Cheshmikhani
IXIAM: ISA EXtension for Integrated Accelerator Management. IEEE Access 11: 33768-33791 (2023) - [j4]Mirco Mannino
Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. IEEE Access 11: 57514-57528 (2023) - [c4]Mirco Mannino
Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. CF 2023: 84-90 - 2022
- [j3]Elham Cheshmikhani
A General Framework for Accelerator Management Based on ISA Extension. IEEE Access 10: 120702-120713 (2022) - [j2]Biagio Peccerillo
A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. J. Syst. Archit. 129: 102561 (2022) - 2021
- [c3]Andrea Mondelli, Paul Gazzillo
SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels. DAC 2021: 973-978 - 2020
- [i2]Andrea Mondelli, Paul Gazzillo, Yan Solihin:
SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels. CoRR abs/2006.16345 (2020) - [i1]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
2010 – 2019
- 2017
- [b1]Andrea Mondelli:
Revisiting Wide Superscalar Microarchitecture. University of Rennes 1, France, 2017 - 2015
- [j1]Pierre Michaud
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. ACM Trans. Archit. Code Optim. 12(3): 28:1-28:22 (2015) - [c2]Nam Ho, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero
Enhancing an x86_64 multi-core architecture with data-flow execution support. Conf. Computing Frontiers 2015: 41:1-41:2 - [c1]Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. DSD 2015: 526-529
Coauthor Index
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