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Chaoyang Zheng
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2020 – today
- 2024
- [j3]Yun Xing
, Chaoyang Zheng
Global exponential synchronization of complex networks with reaction diffusions and finite distributed delays coupling. Neurocomputing 590: 127765 (2024) - [j2]Cong Tao
A Low-Power, Compact, 0.1-5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR. IEEE J. Solid State Circuits 59(9): 2761-2773 (2024) - 2023
- [c3]Chaoyang Zheng, Zhipeng Chen, Jianhua Lu, Yan Ma, Yumei Huang, Zhiliang Hong:
A 400M-510MHz On-Chip Transformer-Based RF Power Amplifier with 22.5dBm Output Power and 48% PAE. ASICON 2023: 1-4 - 2021
- [c2]Xiaofei Qin, Minmin Xu, Chaoyang Zheng, Changxiang He, Xuedian Zhang:
Multi-Scale Feedback Feature Refinement U-Net for Medical Image Segmentation. ICME 2021: 1-6
2010 – 2019
- 2016
- [j1]Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa:
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. IEEE J. Solid State Circuits 51(1): 79-91 (2016) - 2015
- [c1]Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3
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last updated on 2024-09-21 23:34 CEST by the dblp team
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