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Ganesh Balamurugan
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2020 – today
- 2024
- [j14]Cooper S. Levy
, Zhe Xuan
8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter. IEEE J. Solid State Circuits 59(3): 690-701 (2024) - 2023
- [c24]Cooper Levy, Zhe Xuan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Taehwan Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Jinyong Kim, Xinru Wu, Ganesh Balamurugan, Haisheng Rong, James E. Jaussi:
A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter. CICC 2023: 1-2 - [c23]Xinru Wu, Duanni Huang, Taehwan Kim, Ranjeet Kumar, Guan-Lin Su, Chaoxuan Ma, Songtao Liu, Ganesh Balamurugan, Haisheng Rong:
integrated dual-polarization silicon photonic transceiver with automated polarization control. OFC 2023: 1-3 - [c22]Zhe Xuan, Ganesh Balamurugan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Cooper Levy, Jinyong Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Xinru Wu, Tolga Acikalin, Haisheng Rong, James E. Jaussi:
A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-based DWDM Receiver Suitable for In-Package Optical I/O. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j13]Hao Li
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS. IEEE J. Solid State Circuits 57(1): 44-53 (2022) - [j12]Jahnavi Sharma
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS. IEEE J. Solid State Circuits 57(4): 1187-1198 (2022) - [j11]Saeid Daneshgar
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS. IEEE J. Solid State Circuits 57(5): 1397-1408 (2022) - [c21]Hao Li, Meer Nazmus Sakib, Duanni Huang, Ranjeet Kumar, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi:
A 106 Gb/s 2.5 Vppd Linear Microring Modulator Driver with Integrated Photocurrent Sensor in 28nm CMOS. OFC 2022: 1-3 - 2021
- [j10]Hao Li
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control. IEEE J. Solid State Circuits 56(1): 19-29 (2021) - [c20]Hao Li, Zhe Xuan, Ranjeet Kumar, Meer Sakib, Jahnavi Sharma, Chun-Ming Hsu, Chaoxuan Ma, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi:
A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC. ECOC 2021: 1-3 - [c19]Hao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James E. Jaussi:
11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS. ISSCC 2021: 190-192 - [c18]Jahnavi Sharma, Hao Li, Zhe Xuan, Ranjeet Kumar, Chun-Ming Hsu, Meer Sakib, Peicheng Liao, Haisheng Rong, James E. Jaussi, Ganesh Balamurugan:
Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c17]Hao Li, Ganesh Balamurugan, Meer Sakib, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper:
12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control. ISSCC 2020: 208-210
2010 – 2019
- 2019
- [c16]Ganesh Balamurugan, Ajay Balankutty, Chun-Ming Hsu:
56G/112G Link Foundations Standards, Link Budgets & Models. CICC 2019: 1-95 - [c15]Hao Li, Ganesh Balamurugan, Meer Sakib, Jie Sun, Jeffery Driscoll, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper:
A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver. OFC 2019: 1-3 - 2018
- [c14]Hao Li, Ganesh Balamurugan, James E. Jaussi, Bryan Casper:
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. ESSCIRC 2018: 238-241 - 2015
- [c13]Rajesh Inti, Sudip Shekhar, Ganesh Balamurugan, James E. Jaussi, Clark Roberts, Tzu-Chien Hsueh, Bryan Casper:
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS. VLSIC 2015: 346- - 2014
- [j9]Tawfiq Musah
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. IEEE J. Solid State Circuits 49(12): 3079-3090 (2014) - [c12]James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. ISSCC 2014: 440-441 - [c11]Tzu-Chien Hsueh, Ganesh Balamurugan, James E. Jaussi, Sami Hyvonen, Joseph T. Kennedy, Gökçe Keskin, Tawfiq Musah
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS. ISSCC 2014: 444-445 - 2013
- [j8]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. IEEE J. Solid State Circuits 48(12): 3229-3242 (2013) - [c10]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. ISSCC 2013: 402-403 - 2010
- [j7]Frank O'Mahony, James E. Jaussi, Joseph T. Kennedy, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. IEEE J. Solid State Circuits 45(12): 2828-2837 (2010) - [c9]Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. ISSCC 2010: 156-157 - [c8]Ganesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Bryan Casper:
A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS. ISSCC 2010: 372-373
2000 – 2009
- 2009
- [j6]Sudip Shekhar, Ganesh Balamurugan, David J. Allstot, Mozhgan Mansuri, James E. Jaussi, Randy Mooney, Joseph T. Kennedy, Bryan Casper, Frank O'Mahony:
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1818-1829 (2009) - 2008
- [j5]Ganesh Balamurugan, Joseph T. Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney:
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. IEEE J. Solid State Circuits 43(4): 1010-1019 (2008) - [j4]Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag:
Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 314-318 (2008) - [c7]Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper:
Strong injection locking of low-Q LC oscillators. CICC 2008: 699-702 - [c6]Frank O'Mahony, Sudip Shekhar, Mozhgan Mansuri, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Bryan Casper, David J. Allstot, Randy Mooney:
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. ISSCC 2008: 452-453 - 2007
- [c5]Bryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri:
Future Microprocessor Interfaces: Analysis, Design and Optimization. CICC 2007: 479-486 - 2005
- [j3]James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph T. Kennedy, Naresh R. Shanbhag, Randy Mooney:
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. IEEE J. Solid State Circuits 40(1): 80-88 (2005) - [c4]Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan:
Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647 - 2004
- [b1]Ganesh Balamurugan:
Noise-Tolerant Digital System Design. University of Illinois Urbana-Champaign, USA, 2004 - 2003
- [c3]Ganesh Balamurugan, Naresh R. Shanbhag:
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD 2003: 254-260 - 2002
- [j2]Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits 37(5): 624-632 (2002) - 2001
- [j1]Ganesh Balamurugan, Naresh R. Shanbhag:
The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid State Circuits 36(2): 273-280 (2001) - 2000
- [c2]Ganesh Balamurugan, Naresh R. Shanbhag:
A noise-tolerant dynamic circuit design technique. CICC 2000: 425-428
1990 – 1999
- 1999
- [c1]Ganesh Balamurugan, Naresh R. Shanbhag:
Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED 1999: 24-29
Coauthor Index
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