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Yao Xin
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2020 – today
- 2024
- [j12]Xiao Zheng
, Yan Liu
A novel low-latency scheduling approach of TSN for multi-link rate networking. Comput. Networks 240: 110184 (2024) - [j11]Yao Xin
Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA. IEEE/ACM Trans. Netw. 32(2): 1707-1722 (2024) - [c12]Lu Cao
Bubble Sketch: A High-performance and Memory-efficient Sketch for Finding Top-k Items in Data Streams. CIKM 2024: 3653-3657 - 2023
- [j10]Yao Xin
A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. IEEE Micro 43(2): 110-119 (2023) - [c11]Alessandro Aliberti
Comparative analysis of neural networks techniques to forecast Airfare Prices. COMPSAC 2023: 1023-1029 - [c10]Zengxie Ma, Ning Hu, Bo Qu, Yao Xin, Shengan Song, Xinyi Qiu:
Building a High-Performance Data Channel for the Federal Cyber Range. DSC 2023: 16-23 - [c9]Yan Liu
MCCQF: Low-Latency Transmission Based on IEEE 802.1 Qch For Hierarchical Networking. ICC 2023: 6052-6058 - [i1]Yao Xin, Guoming Tang, Donglong Chen, Rumin Zhang, Teng Liang, Ray C. C. Cheung, Çetin Kaya Koç:
A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection. CoRR abs/2306.11351 (2023) - 2022
- [j9]Yao Xin
High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection. IEEE Trans. Computers 71(7): 1507-1521 (2022) - [j8]Yao Xin
FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree. IEEE/ACM Trans. Netw. 30(6): 2760-2775 (2022) - [c8]Yuxi Liu, Yao Xin, Wenjun Li
HybridTSS: A Recursive Scheme Combining Coarse- and Fine- Grained Tuples for Packet Classification. APNet 2022: 43-49 - [c7]Yao Xin, Wenjun Li, Gaogang Xie, Yang Xu, Yi Wang:
Updatable Packet Classification on FPGA with Bounded Worst-Case Performance. HOTI 2022: 21-28 - [c6]Yao Xin, Guoming Tang, Donglong Chen, Rumin Zhang, Teng Liang, Ray C. C. Cheung, Çetin Kaya Koç:
A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection. SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta 2022: 540-549 - 2021
- [c5]Yao Xin, Yuxi Liu, Wenjun Li, Ruyi Yao, Yang Xu
KickTree: A Recursive Algorithmic Scheme for Packet Classification with Bounded Worst-Case Performance. ANCS 2021: 23-30 - [c4]Yao Xin, Wenjun Li, Yi Wang, Song Yao:
An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets. INFOCOM Workshops 2021: 1-2
2010 – 2019
- 2016
- [j7]Zhaorui Zhang
FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery. Frontiers Robotics AI 3: 51 (2016) - [j6]Will X. Y. Li, Ray C. C. Cheung
An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis. J. Circuits Syst. Comput. 25(1): 1640004:1-1640004:21 (2016) - 2015
- [j5]Yao Xin, Will X. Y. Li, Zhaorui Zhang
An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics. IEEE ACM Trans. Comput. Biol. Bioinform. 12(5): 1034-1047 (2015) - 2014
- [j4]Benben Liu, Yao Xin, Ray C. C. Cheung
GPU-based biclustering for microarray data analysis in neurocomputing. Neurocomputing 134: 239-246 (2014) - [j3]Yao Xin, Will X. Y. Li, Ray C. C. Cheung
An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking. Microelectron. J. 45(6): 690-701 (2014) - [c3]Will X. Y. Li, Yao Xin, Rosa H. M. Chan, Dong Song
Laguerre-volterra model and architecture for MIMO system identification and output prediction. EMBC 2014: 4539-4542 - [c2]Will X. Y. Li, Yao Xin, Dong Song
VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel. ISIC 2014: 272-275 - 2013
- [j2]Yan Q. You, Tao Jie, Yao Xin:
Erratum to "Finding the most efficient DMUs in DEA: An improved integrated model" [Comput. Indus. Eng. 52 (2007) 71-77]. Comput. Ind. Eng. 66(4): 1178-1179 (2013) - [j1]Yao Xin, Benben Liu, Biao Min, Will X. Y. Li, Ray C. C. Cheung
Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform. Microelectron. J. 44(8): 670-682 (2013) - [c1]Yao Xin, Will X. Y. Li, Biao Min, Yan Han, Ray C. C. Cheung
A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity. EMBC 2013: 4993-4996
Coauthor Index
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