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Yuhwan Ro
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2020 – today
- 2024
- [j5]Byeongho Kim
, Sanghoon Cha, Sangsoo Park, Jieun Lee, Sukhan Lee, Shinhaeng Kang, Jinin So
The Breakthrough Memory Solutions for Improved Performance on LLM Inference. IEEE Micro 44(3): 40-48 (2024) - 2023
- [c7]Jin Hyun Kim, Yuhwan Ro, Jinin So, Sukhan Lee, Shinhaeng Kang, YeonGon Cho, Hyeonsu Kim, Byeongho Kim, Kyungsoo Kim, Sangsoo Park, Jin-Seong Kim, Sanghoon Cha, Won-Jo Lee, Jin Jung, Jonggeon Lee, Jieun Lee, Joon-Ho Song, Seungwon Lee, Jeonghyeon Cho, Jaehoon Yu, Kyomin Sohn:
Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster. HCS 2023: 1-31 - 2022
- [j4]Jin Hyun Kim
Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer. IEEE Micro 42(3): 20-30 (2022) - 2021
- [c6]Jin Hyun Kim, Shinhaeng Kang, Sukhan Lee, Hyeonsu Kim, Woongjae Song, Yuhwan Ro, Seungwon Lee, David Wang, Hyunsung Shin, BengSeng Phuah, Jihyun Choi, Jinin So, YeonGon Cho, Joon-Ho Song, Jangseok Choi, Jeonghyeon Cho, Kyomin Sohn, Young-Soo Sohn, Kwang-Il Park, Nam Sung Kim:
Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond. HCS 2021: 1-26 - [c5]Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim:
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. ISSCC 2021: 350-352
2010 – 2019
- 2019
- [c4]Jongwook Chung, Yuhwan Ro, Joonsung Kim, Jaehyung Ahn, Jangwoo Kim, John Kim
Enforcing Last-Level Cache Partitioning through Memory Virtual Channels. PACT 2019: 97-109 - 2018
- [j3]Sukhan Lee, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim, Jung Ho Ahn
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. IEEE Access 6: 31387-31398 (2018) - 2017
- [j2]Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. IEEE Comput. Archit. Lett. 16(1): 76-79 (2017) - [j1]Yuhwan Ro, Min Chul Sung, Yongjun Park, Jung Ho Ahn
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems. IEICE Electron. Express 14(11): 20170437 (2017) - [c3]Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. HPCA 2017: 517-528 - [c2]Sukhan Lee, Yuhwan Ro, Young Hoon Son, Hyunyoon Cho, Nam Sung Kim, Jung Ho Ahn
Understanding power-performance relationship of energy-efficient modern DRAM devices. IISWC 2017: 110-111 - 2013
- [c1]Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn
Reducing memory access latency with asymmetric DRAM bank organizations. ISCA 2013: 380-391
Coauthor Index
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last updated on 2024-09-28 01:29 CEST by the dblp team
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