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Varadan Savulimedu Veeravalli
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2010 – 2019
- 2017
- [j3]Varadan Savulimedu Veeravalli, Andreas Steininger
, Ulrich Schmid:
A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems 53: 130-144 (2017) - [c12]Marko S. Andjelkovic
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS 2017: 82-87 - [c11]Bernhard Fritz, Andreas Steininger
Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD 2017: 329-336 - 2016
- [c10]Varadan Savulimedu Veeravalli, Andreas Steininger
Design and Physical Implementation of a Target ASIC for SET Experiments. DSD 2016: 694-697 - [c9]Varadan Savulimedu Veeravalli, Andreas Steininger
Study of a delayed single-event effect in the Muller C-element. ETS 2016: 1-2 - 2015
- [j2]Andreas Steininger
Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik 132(6): 301-306 (2015) - [c8]Varadan Savulimedu Veeravalli, Andreas Steininger
Reliable and Continuous Measurement of SET Pulse Widths. DSD 2015: 181-188 - 2014
- [c7]Andreas Steininger
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD 2014: 61-67 - [c6]Varadan Savulimedu Veeravalli, Andreas Steininger
Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED 2014: 236-242 - [c5]Varadan Savulimedu Veeravalli, Andreas Steininger
Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED 2014: 412-419 - 2013
- [j1]Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37(8-A): 772-791 (2013) - [c4]Jakob Lechner, Varadan Savulimedu Veeravalli:
Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC 2013: 23-30 - 2012
- [c3]Varadan Savulimedu Veeravalli, Andreas Steininger
Radiation-tolerant combinational gates - an implementation based comparison. DDECS 2012: 115-120 - [c2]Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD 2012: 8-17 - [c1]Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger
Protecting an Asynchronous NoC against Transient Channel Faults. DSD 2012: 264-271
Coauthor Index
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