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Lavanya Subramanian
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2020 – today
- 2024
- [c14]Armand Behroozi
, Yuxiang Chen
SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping. ASPLOS (3) 2024: 900-915 - 2023
- [j6]Behzad Boroujerdian
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity. ACM Trans. Embed. Comput. Syst. 22(2): 31:1-31:35 (2023) - 2022
- [i11]Behzad Boroujerdian, Ying Jing, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi:
FARSI: Facebook AR System Investigator for Agile Domain-Specific System-on-Chip Exploration. CoRR abs/2201.05232 (2022) - 2020
- [c13]Damla Senol Cali
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis. MICRO 2020: 951-966 - [i10]Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gómez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, Onur Mutlu:
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis. CoRR abs/2009.07692 (2020)
2010 – 2019
- 2019
- [c12]Ram Srivatsa Kannan, Lavanya Subramanian, Ashwin Raju, Jeongseob Ahn
GrandSLAm: Guaranteeing SLAs for Jobs in Microservices Execution Frameworks. EuroSys 2019: 34:1-34:16 - 2018
- [c11]Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. DAC 2018: 170:1-170:6 - [c10]Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147 - [i9]Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian, Kevin K. Chang, Onur Mutlu:
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems. CoRR abs/1804.11043 (2018) - [i8]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost. CoRR abs/1805.03048 (2018) - [i7]Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu:
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems. CoRR abs/1805.05926 (2018) - 2017
- [j5]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. Proc. ACM Meas. Anal. Comput. Syst. 1(1): 26:1-26:36 (2017) - [c9]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. SIGMETRICS (Abstracts) 2017: 54 - 2016
- [j4]Lydia Kyei-Blankson, Kamakshi S. Iyer, Lavanya Subramanian:
Social Networking Sites: College Students' Patterns of Use and Concerns for Privacy and Trust by Gender, Ethnicity, and Employment Status. Int. J. Inf. Commun. Technol. Educ. 12(4): 62-75 (2016) - [j3]Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, Onur Mutlu:
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. ACM Trans. Archit. Code Optim. 12(4): 65:1-65:28 (2016) - [j2]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling. IEEE Trans. Parallel Distributed Syst. 27(10): 3071-3087 (2016) - [i6]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM (TL-DRAM). CoRR abs/1601.06903 (2016) - [i5]Kevin Kai-Wei Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert, Mike O'Connor, Srilatha Manne, Lisa Hsu, Lavanya Subramanian, Onur Mutlu:
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism. CoRR abs/1602.00722 (2016) - [i4]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu:
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. CoRR abs/1610.09604 (2016) - 2015
- [c8]Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, Onur Mutlu:
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM. PACT 2015: 174-187 - [c7]Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Manabi Khan, Onur Mutlu:
The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory. MICRO 2015: 62-75 - [c6]Hui Wang, Canturk Isci, Lavanya Subramanian, Jongmoo Choi, Depei Qian, Onur Mutlu:
A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters. VEE 2015: 93-106 - [i3]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity. CoRR abs/1504.00390 (2015) - [i2]Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, Onur Mutlu:
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. CoRR abs/1505.07502 (2015) - [i1]Lavanya Subramanian:
Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management. CoRR abs/1508.03087 (2015) - 2014
- [j1]Onur Mutlu, Lavanya Subramanian:
Research Problems and Opportunities in Memory Systems. Supercomput. Front. Innov. 1(3): 19-55 (2014) - [c5]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost. ICCD 2014: 8-15 - 2013
- [c4]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-latency DRAM: A low latency and low cost DRAM architecture. HPCA 2013: 615-626 - [c3]Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu:
MISE: Providing performance predictability and improving fairness in shared main memory systems. HPCA 2013: 639-650 - 2012
- [c2]Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu:
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. ISCA 2012: 416-427 - 2011
- [c1]Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda:
Reducing memory interference in multicore systems via application-aware memory channel partitioning. MICRO 2011: 374-385
Coauthor Index
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