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Wai-Shing Luk
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Journal Articles
- 2020
- [j12]Yunhui Qiu
, Jinyu Xie, Hankun Lv, Wenbo Yin, Wai-Shing Luk, Lingli Wang
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA. IEEE Trans. Parallel Distributed Syst. 31(8): 1828-1444 (2020) - 2018
- [j11]Ye Zhang
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - 2017
- [j10]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - 2016
- [j9]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - 2015
- [j8]Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng:
Multi-parameter clock skew scheduling. Integr. 48: 129-137 (2015) - [j7]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - 2013
- [j6]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng:
SmipRef: An efficient method for multi-domain clock skew scheduling. Integr. 46(4): 392-403 (2013) - 2012
- [j5]Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng:
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2172-2181 (2012) - 2009
- [j4]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1652-1659 (2009) - [j3]Qiang Fu, Wai-Shing Luk, Jun Tao, Xuan Zeng, Wei Cai:
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3007-3015 (2009) - 1997
- [j2]Wai-Shing Luk, Omar Wing:
Waveform Krylov Subspace Methods on a Massively Parallel Computer. Int. J. High Speed Comput. 9(1): 73-84 (1997) - [j1]Tien-Tsin Wong, Wai-Shing Luk, Pheng-Ann Heng:
Sampling with Hammersley and Halton Points. J. Graphics, GPU, & Game Tools 2(2): 9-24 (1997)
Conference and Workshop Papers
- 2024
- [c16]Shaoyang Sun, Boyin Jin, Jiahang Lou, Jiangnan Li, Yuhang Cao, Jingyuan Li, Chen Shen, Yuan Dai, Wenbo Yin, Wai-Shing Luk, Lingli Wang:
MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes. ASAP 2024: 133-134 - [c15]Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang:
CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. FPL 2024: 213-219 - 2021
- [c14]Jingbo Gao, Yu Qian
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. FPT 2021: 1-9 - 2017
- [c13]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c12]Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Layout decomposition for hybrid E-beam and DSA double patterning lithography. ISCAS 2017: 1-4 - 2015
- [c11]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC 2015: 652-657 - 2013
- [c10]Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD 2013: 170-177 - 2011
- [c9]Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng:
An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369 - 2010
- [c8]Wai-Shing Luk, Huiping Huang:
Fast and lossless graph division method for layout decomposition using SPQR-tree. ICCAD 2010: 112-115 - 2008
- [c7]Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. DAC 2008: 223-226 - [c6]Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. ISQED 2008: 718-723 - 2007
- [c5]Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng:
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. ASP-DAC 2007: 203-208 - [c4]Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng:
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. ASP-DAC 2007: 209-214 - 1997
- [c3]Wai-Shing Luk, Tien-Tsin Wong:
Two New Quorum Based Algorithms for Distributed Mutual Exclusion. ICDCS 1997: 100-106 - 1995
- [c2]Wai-Shing Luk, Omar Wing:
The Use of Inexact ODE Solver in Waveform Relaxation Methods on a Massively Parallel Computer. PP 1995: 385-390 - 1994
- [c1]Tien Chi Chen, Wai-Shing Luk:
Aberth's Method for the Parallel Iterative Finding of Polynomial Zeros. APL 1994: 40-49
Coauthor Index
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