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Maciej Bellos
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2000 – 2009
- 2006
- [j2]Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52(1): 1-12 (2006) - 2005
- [b1]Maciej Bellos:
Τεχνικές ελέγχου ορθής λειτουργίας με έμφαση στη χαμηλή κατανάλωση ισχύος. University of Patras, Greece, 2005 - [c10]Maciej Bellos, Dimitris Nikolos:
Deterministic Test Vector Compression / Decompression Using an Embedded Processor. EDCC 2005: 318-331 - 2004
- [c9]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED 2004: 205-210 - [c8]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST. ISVLSI 2004: 281-284 - [c7]Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI 2004: 285-288 - 2003
- [j1]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003) - [c6]Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos:
Low Power Test Set Embedding Based on Phase Shifters. ISVLSI 2003: 155-160 - [c5]Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris:
DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC 2003: 343- - 2002
- [c4]Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos:
Test Set Embedding Based on Phase Shifters. EDCC 2002: 90-101 - 2001
- [c3]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247
1990 – 1999
- 1999
- [c2]Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC 1999: 267-282 - [c1]Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos:
Path delay fault testing of Benes multistage interconnection networks. ICECS 1999: 1097-1100
Coauthor Index
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