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Nikola Nedovic
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2020 – today
- 2024
- [j9]Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59(4): 1146-1157 (2024) - [c20]Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray:
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. ISSCC 2024: 302-304 - 2023
- [j8]Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58(4): 1062-1073 (2023) - [c19]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c18]Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray:
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. VLSI Technology and Circuits 2022: 146-147 - [c17]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits 2022: 154-155 - 2020
- [c16]Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC 2020: 126-128
2010 – 2019
- 2019
- [j7]John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54(1): 43-54 (2019) - [c15]Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen G. Tell, C. Thomas Gray:
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. CICC 2019: 1-4 - [c14]Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - [c13]Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray:
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC 2019: 81 - 2018
- [c12]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c11]John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC 2018: 276-278 - 2014
- [c10]Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto:
A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology. A-SSCC 2014: 377-380 - 2010
- [j6]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010)
2000 – 2009
- 2008
- [j5]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3038-3049 (2008) - 2007
- [j4]Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. IEEE J. Solid State Circuits 42(6): 1392-1404 (2007) - [j3]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42(12): 2726-2735 (2007) - [c9]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC 2007: 224-598 - 2006
- [c8]Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. PATMOS 2006: 360-369 - 2005
- [j2]Nikola Nedovic, Vojin G. Oklobdzija:
Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 577-590 (2005) - [c7]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732 - 2004
- [j1]Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija:
A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits 39(8): 1294-1304 (2004) - 2002
- [c6]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) 2002: 105-108 - [c5]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED 2002: 56-59 - 2001
- [c4]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Timing Characterization of Dual-edge Triggered Flip-flops. ICCD 2001: 538-541 - [c3]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional techniques for low power consumption flip-flops. ICECS 2001: 803-806 - 2000
- [c2]Nikola Nedovic, Vojin G. Oklobdzija:
Dynamic Flip-Flop with Improved Power. ICCD 2000: 323-326 - [c1]Nikola Nedovic, Vojin G. Oklobdzija:
Hybrid latch Flip-Flop with Improved Power Efficiency. SBCCI 2000: 211-215
Coauthor Index
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