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SIGARCH Computer Architecture News, Volume 41
Volume 41, Number 1, March 2013
- Vivek Sarkar, Rastislav Bodík:
Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, Houston, TX, USA, March 16-20, 2013. ACM 2013, ISBN 978-1-4503-1870-9 [contents]
Volume 41, Number 2, May 2013
- Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty:
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. 1-8 - Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha:
Performance analysis of a FPGA based novel binary and DBNS multiplier. 9-16 - Michael Sartin-Tarm, Tony Nowatzki, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan:
Constraint centric scheduling guide. 17-21 - Apala Guha, Yao Zhang, Raihan Ur Rasool
, Andrew A. Chien:
Systematic evaluation of workload clustering for extremely energy-efficient architectures. 22-29 - Amrita Saha, Pijush Biswas, Amitabha Sinha:
An integrated development platform of a reconfigurable radio processor for software defined radio. 30-35 - Santanu Pal, Amitabha Sinha, Pijush Biswas:
FPGA implementation of a novel DCT architecture reducing constant cosine terms. 36-40 - Kuo-Kun Tseng, FuFu Zeng, Huang-Nan Huang, Yiming Liu, Jeng-Shyang Pan, W. H. Ip
A new non-exact Aho-Corasick framework for ECG classification. 41-46 - Subhashis Maitra, Amitabha Sinha:
High performance MAC unit for DSP and cryptographic applications. 47-55
- Mark Thorson:
Internet nuggets. 56-71
Volume 41, Number 3, June 2013
- Avi Mendelson:
The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013. ACM 2013, ISBN 978-1-4503-2079-5 [contents]
Volume 41, Number 4, September 2013
- Subhashis Maitra, Amitabha Sinha:
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. 1-7 - Tomislav Janjusic, Krishna M. Kavi:
Gleipnir: a memory profiling and tracing tool. 8-12
- Mark Thorson:
Internet nuggets. 13-22
Volume 41, Number 5, December 2013
- Ivan Godard:
The Mill: split-stream encoding. 1-5 - Alexander Thomasian:
Disk arrays with multiple RAID levels. 6-24 - Subhashis Maitra, Amitabha Sinha:
Design and simulation of MAC unit using combinational circuit and adder. 25-33
- Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. 35-40 - Atabak Mahram, Martin C. Herbordt:
NCBI BLASTP on the convey HC1-EX. 41-46 - Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. 47-52 - Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala:
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. 53-58 - Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont:
Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. 59-64 - Heiner Giefers, Christian Plessl, Jens Förstner:
Accelerating finite difference time domain simulations with reconfigurable dataflow computers. 65-70 - Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
A reconfigurable Java accelerator with software compatibility for embedded systems. 71-76 - Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. 77-82 - Florent de Dinechin, Matei Istoan, Guillaume Sergent:
Fixed-point trigonometric functions on FPGAs. 83-88 - Jubee Tada:
Performance evaluation of 3-D stacked 32-bit parallel multipliers. 89-94 - Yuichiro Tanaka, Shimpei Sato, Kenji Kise:
The Ultrasmall soft processor. 95-100 - Liucheng Guo, David B. Thomas, Wayne Luk:
Customisable architectures for the set covering problem. 101-106 - Gary Plumbridge, Jack Whitham, Neil C. Audsley:
Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators. 107-117 - Chuan Hong, Khaled Benkrid, Mohd Nazrin Md. Isa, Xabier Iturbe
A run-time reconfigurable system for adaptive high performance efficient computing. 113-118
- Mark Thorson:
Internet nuggets. 119-127
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