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Microprocessors and Microsystems, Volume 47
Volume 47, Part A, November 2016
- Lilian Bossuet, Giorgio Di Natale, Paris Kitsos
:
Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE). 1-2 - Mario Barbareschi
Ring oscillators analysis for security purposes in Spartan-6 FPGAs. 3-10 - Edward Jung
Identification of IP control units by state encoding and side channel verification. 11-22 - Simon Pontie
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. 23-36 - Noemie Beringuier-Boher, Vincent Beroulle, David Hély
Clock generator behavioral modeling for supply voltage glitch attack effects analysis. 37-43 - Brice Colombier, Lilian Bossuet, David Hély
From secured logic to IP protection. 44-54 - Filip Kodýtek
Improved ring oscillator PUF on FPGA and its properties. 55-63 - Athanasios Papadimitriou
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. 64-73 - Hermann Seuschek, Stefan Rass
Side-channel leakage models for RISC instruction set architectures from empirical data. 74-81 - Martin Petrvalsky, Milos Drutarovský
Constant-weight coding based software implementation of DPA countermeasure in embedded microcontroller. 82-89
- Weizhe Zhang, Albert M. K. Cheng
Special Issue on Real-Time Scheduling on Heterogeneous Multi-core Processors. 90-92 - Guoqi Xie, Gang Zeng, Liangjiao Liu, Renfa Li, Keqin Li:
Mixed real-time scheduling of multiple DAGs-based applications on heterogeneous multi-core processors. 93-103 - Xuehe Zhang, Ge Li, Gangfeng Liu, Jie Zhao, ZhenXiu Hou:
GPU based real-time SLAM of six-legged robot. 104-111 - Jun Guo, Anxiang Ma, Yongming Yan, Bin Zhang:
Application performance prediction method based on cross-core performance interference on multi-core processor. 112-120 - Bocheng Liu, Qingkui Chen, Jinjing Li, Liping Gao:
Ai BCS: A GPU cluster scheduling optimization based on SKE model. 121-132 - Yatong Jiang, Seungmin Rho, Yingping Zhang, Feng Jiang, Jian Yin:
Multi-scale stream reduction for volume rendering on GPUs. 133-141 - Ge Li, Xuehe Zhang, Changle Li, HongZhe Jin, Jie Zhao:
Design and application of parallel stereo matching algorithm based on CUDA. 142-150 - Wenjing Li, Yingzhou Bi, Xiaofeng Zhu
Hybrid swarm intelligent parallel algorithm research based on multi-core clusters. 151-160 - Jiaxuan Wu, Changsheng Zhang, Bin Zhang, Peng Wang:
A new data-grouping-aware dynamic data placement method that take into account jobs execute frequency for Hadoop. 161-169 - Haifeng Song
The improved (2D)2PCA algorithm and its parallel implementation based on image block. 170-177 - Yuliang Shi, Kaihui Zhang, Lizhen Cui, Lei Liu, Yongqing Zheng, Shidong Zhang, Han Yu
MapReduce short jobs optimization based on resource reuse. 178-187 - Yongming Yan, Bin Zhang, Jun Guo:
Research on the selection method of multi-VM resource adjustment strategy in a single PM based on genetic algorithm. 188-197 - Wenbin Zhang, Yuliang Shi, Lei Liu, Shidong Zhang, Yongqing Zheng, Lizhen Cui, Han Yu
CTP: A scheduling strategy to smooth response time fluctuations in multi-tier website system. 198-208 - Yatao Yang, Chao Wu, Zichen Li, Junming Yang:
Efficient FPGA implementation of modular multiplication based on Montgomery algorithm. 209-215 - Hrishikesh Salunkhe
Modeling & analysis of an LTE-Advanced receiver using mode-controlled dataflow. 216-230 - Pham Nam Khanh, Akash Kumar
Leakage aware resource management approach with machine learning optimization framework for partially reconfigurable architectures. 231-243 - Jian Wang, Chang Liu, Wenfeng Li, Kaiyuan Li:
Heterogeneous multi-mode access in smart grid using BeiDou communication. 244-249
Volume 47, Part B, November 2016
- Francesco Leporati, Lech Józwiak:
Special Section on European Projects in Embedded System Design 2015. 251 - Réda Nouacer, Manel Djemal, Smaïl Niar
EQUITAS: A tool-chain for functional safety and reliability improvement in automotive systems. 252-261 - Carlos Álvarez
The AXIOM software layers. 262-277 - Kerstin Eder, John P. Gallagher
ENTRA: Whole-systems energy transparency. 278-286 - Leonidas Kosmidis
Fitting processor architectures for measurement-based probabilistic timing analysis. 287-302 - Giordana Florimbi
The Human Brain Project: Parallel technologies for biologically accurate simulation of Granule cells. 303-313
- Fynn Schwiegelshohn, Eugen Ossovski, Michael Hübner:
A resampling method for parallel particle filter architectures. 314-320 - Yaman Umuroglu, Magnus Jahre
Random access schemes for efficient FPGA SpMV acceleration. 321-332
- Mohamed Amine Boussadi, Thierry Tixier, Alexis Landrault, Jean-Pierre Dérutin:
HNCP: A many-core microprocessor ASIC approach dedicated to embedded image processing applications. 333-346 - Jan Malburg, Alexander Finder, Görschwin Fey
Debugging hardware designs using dynamic dependency graphs. 347-359 - Hokyoon Lee, Yoonah Paik, Jaeyung Jun, Youngsun Han
High-throughput low-area design of AES using constant binary matrix-vector multiplication. 360-368 - Somaia Awad Hassan, A. M. Hemeida, Mountasser M. M. Mahmoud:
Performance Evaluation of Matrix-Matrix Multiplications Using Intel's Advanced Vector Extensions (AVX). 369-374 - Arcangelo Sisto, Luca Pilato
Application specific instruction set processor for sensor conditioning in automotive applications. 375-384 - Junjie Peng, Xiaofei Zhi, Xiaolan Xie:
Application type based resource allocation strategy in cloud environment. 385-391 - Julio Pérez Acle
Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation. 392-403 - M. Mohamed Asan Basiri
An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform. 404-418 - Daolu Zha, Xi Jin, Tian Xiang:
A real-time global stereo-matching on FPGA. 419-428 - Abdul-Malik H. Y. Saad
High-speed implementation of fractal image compression in low cost FPGA. 429-440 - Encarnación Castillo
Comments on "Fast architecture for decimal digit multiplication". 441-444 - Abdulaziz Eker, Yakup Murat Mert, Oguz Ergin
URFA-Update based register file architecture with partial register write for energy efficiency. 445-453 - Atiyeh Panahi, Fazel Sharifi, Mohammad Hossein Moaiyeri
CNFET-based approximate ternary adders for energy-efficient image processing applications. 454-465 - Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer:
VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. 466-485 - Lei Yi, Guangbao Shan
High-performance processor design based on 3D on-chip cache. 486-490
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