default search action
Microprocessors and Microsystems - Embedded Hardware Design, Volume 35
Volume 35, Number 1, February 2011
- Amir Hasanbegovic, Snorre Aunet:
Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process. 1-9 - Qinma Kang, Hong He:
A novel discrete particle swarm optimization algorithm for meta-task assignment in heterogeneous computing systems. 10-17 - Xianwen Yang, Zheng Li, An Wang, Shengjun Wen:
Design research of the DES against power analysis attacks based on FPGA. 18-22 - Zdenka Babic, Aleksej Avramovic, Patricio Bulic:
An iterative logarithmic multiplier. 23-33 - Abdulhadi Shoufan
, Nico Huber, H. Gregor Molter
A novel cryptoprocessor architecture for chained Merkle signature scheme. 34-47 - Jung-Wook Park
A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk. 48-59 - Wenguo Liu, Alan F. T. Winfield
Open-hardware e-puck Linux extension board for experimental swarm robotics research. 60-67 - Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses. 68-80
- Amir Muhammad, Michael J. Pont:
Comments on: "Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols". 81-82
Volume 35, Number 2, March 2011
- Maurizio Palesi
Network-on-chip architectures and design methodologies. 83-84 - Wei Song
Asynchronous spatial division multiplexing router. 85-97 - Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang:
A practical low-latency router architecture with wing channel for on-chip network. 98-109 - Yixuan Zhang, Randy Wayne Morris Jr., Avinash Karanth Kodi:
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture. 110-118 - Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu:
On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks. 119-129 - Radu Andrei Stefan, Kees Goossens:
A TDM slot allocation flow based on multipath routing in NoCs. 130-138 - Chris Jackson, Simon J. Hollis:
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip. 139-151 - Dmitri Vainbrand, Ran Ginosar:
Scalable network-on-chip architecture for configurable neural networks. 152-166 - Maurizio Martina, Guido Masera
On chip interconnects for multiprocessor turbo decoding architectures. 167-181 - Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin:
Hierarchical circuit-switched NoC for multicore video processing. 182-199 - Muhammad E. S. Elrabaa, Abdelhafid Bouhraoua:
A hardwired NoC infrastructure for embedded systems on FPGAs. 200-216 - Ning Ma, Zhonghai Lu, Li-Rong Zheng:
System design of full HD MVC decoding on mesh-based multicore NoCs. 217-229 - Francisco Triviño, José L. Sánchez
Virtualizing network-on-chip resources in chip-multiprocessors. 230-245 - Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens:
Design and implementation of an operating system for composable processor sharing. 246-260 - Mario R. Casu
A NoC-based hybrid message-passing/shared-memory approach to CMP design. 261-273 - Martti Forsell:
Performance comparison of some shared memory organizations for 2D mesh-like NOCs. 274-284 - Rishad A. Shafik, Bashir M. Al-Hashimi:
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study. 285-296
Volume 35, Number 3, May 2011
- Nicolas Huber, M. S. Hromalik-Pouchet, Tobia D. Carozzi
Parallel processing speed increase of the one-bit auto-correlation function in hardware. 297-307 - Lei Zhang, Meikang Qiu, Edwin Hsing-Mean Sha, Qingfeng Zhuge:
Variable assignment and instruction scheduling for processor with multi-module memory. 308-317 - Yiqiong Shi, Bah-Hwee Gwee
Asynchronous DSP for low-power energy-efficient embedded systems. 318-328 - Nikolas Kroupis, Dimitrios Soudris
FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer. 329-342 - Faizal Arya Samman
Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip. 343-358 - Gyu Sang Choi, Byung-Won On:
Study of the performance impact of a cache buffer in solid-state disks. 359-369
Volume 35, Number 4, June 2011
- Hongbin Sun, Pengju Ren, Nanning Zheng, Tong Zhang, Tao Li:
Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology. 371-381 - Ji Gu, Hui Guo, Patrick Li:
An on-chip instruction cache design with one-bit tag for low-power embedded systems. 382-391 - Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP). 392-404 - Uros Legat, Anton Biasizzo, Franc Novak:
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources. 405-416 - Sanghamitra Roy
Exploiting dynamic micro-architecture usage in gate sizing. 417-425 - Gustavo Rau de Almeida Callou
Energy consumption and execution time estimation of embedded system applications. 426-440 - André V. Fidalgo
Real-time fault injection using enhanced on-chip debug infrastructures. 441-452
Volume 35, Number 5, July 2011
- Man Ho Kim, Suk Lee, Kyung Chang Lee
A fuzzy predictive redundancy system for fault-tolerance of x-by-wire systems. 453-461 - Giang Nguyen Huong, Yeoul Na, Seon Wook Kim:
Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture. 462-472 - Rabah Sadoun, Adel Belouchrani
An FPGA based soft multiprocessor for DNS/DNSSEC authoritative server. 473-483 - Licheng Xue, Feng Shi, Weixing Ji, Haroon-Ur-Rashid Khan:
3D floorplanning of low-power and area-efficient Network-on-Chip architecture. 484-495 - John A. Kalomiros
Design and hardware implementation of a stereo-matching system based on dynamic programming. 496-509 - Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari:
An embedded multi-core biometric identification system. 510-521
Volume 35, Number 6, August 2011
- Anita Tino, Gul N. Khan
Designing power and performance optimal application-specific Network-on-Chip architectures. 523-534 - Pedro Echeverría, Marisa López-Vallejo
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. 535-546 - Tareq Hasan Khan, Khan A. Wahid:
Universal bridge interface for DVP-compatible image sensors. 547-556 - Antonio Armato, Luca Fanucci
Low-error digital hardware implementation of artificial neuron activation functions and their derivative. 557-567 - J. Manikandan
Design of a real time automatic speech recognition system using Modified One Against All SVM classifier. 568-578 - Sergio Saponara
Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects. 579-592
Volume 35, Number 7, October 2011
- Raija Lehto, Tarja Taurén, Olli Vainio:
Recursive FIR filter structures on FPGA. 595-602 - Thomas Canhao Xu
A study of 3D Network-on-Chip design for data parallel H.264 coding. 603-612 - Claudia Rusu, Lorena Anghel
Adaptive inter-layer message routing in 3D networks-on-chip. 613-631 - Matthias Bo Stuart
Analytical derivation of traffic patterns in cache-coherent shared-memory systems. 632-642 - Khalid Latif, Tiberiu Seceleanu
Service based communication for MPSoC platform-SegBus. 643-655
Volume 35, Number 8, November 2011
- Sebastián López
Preface. 657-658 - Palanichamy Manikandan
Design of embedded TCAM based longest prefix match search engine. 659-667 - Andrea Marongiu, Paolo Burgio
Supporting OpenMP on a multi-cluster embedded MPSoC. 668-682 - Sonia López, Oscar Garnica
A phase adaptive cache hierarchy for SMT processors. 683-694 - Ana Bosque, Víctor Viñals
Filtering directory lookups in CMPs. 695-707 - Malek Naoues, Dominique Noguet, Laurent Alaus, Yves Louët:
A common operator for FFT and FEC decoding. 708-715 - Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit:
Mobile satellite reception with a virtual satellite dish based on a reconfigurable multi-processor architecture. 716-728 - Levent Aksoy
Finding the optimal tradeoff between area and delay in multiple constant multiplications. 729-741 - Antoni Roca, José Flich
A low-latency modular switch for CMP systems. 742-754 - José L. Risco-Martín
Simulation of high-performance memory allocators. 755-765 - Ahmad Patooghy
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips. 766-778
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-16 22:16 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: