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Journal of Systems Architecture, Volume 51
Volume 51, Number 1, January 2005
- Wei Shi, Pradip K. Srimani:
Hierarchical star: a new two level interconnection network. 1-14 - Claude Limousin, Julien Sébot, Alexis Vartanian, Nathalie Drach:
Architecture optimization for multimedia application exploiting data and thread-level parallelism. 15-27 - Ernesto Martins
, Luís Almeida
An FPGA-based coprocessor for real-time fieldbus traffic scheduling - architecture and implementation. 29-44 - Guohui Li, Hongya Wang:
A novel min-process checkpointing scheme for mobile computing systems. 45-61 - Rafael Rico, Juan Ignacio Pérez, José Antonio de Frutos:
The impact of x86 instruction set architecture on superscalar processing. 63-77
Volume 51, Number 2, February 2005
- Xiaofei Liao, Hai Jin:
A new distributed storage scheme for cluster video server. 79-94 - Parag A. Kulkarni
Dual and multiple token based approaches for load balancing. 95-110 - Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities. 111-123 - Jun Ho Park, Myung-Jin Lee, Soon-Ju Kang:
CORBA-based distributed and replicated resource repository architecture for hierarchically configurable home network. 125-142 - Tzung-Shi Chen, Nen-Chung Wang
Optimal broadcasting on incomplete star graph interconnection networks. 143-150
Volume 51, Number 3, March 2005
- Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee:
Instruction level redundant number computations for fast data intensive processing in asynchronous processors. 151-164 - Nen-Chung Wang
Multicast communication in wormhole-routed symmetric networks with hamiltonian cycle model. 165-183 - Yuh-Shyan Chen
A generalized fault-tolerant sorting algorithm on a product network. 185-205 - Nabanita Das:
More on rearrangeability of combined (2n. 207-222
Volume 51, Number 4, April 2005
- Kristof Beyls, Erik H. D'Hollander:
Generating cache hints for improved program efficiency. 223-250 - Francisco J. Villa, Manuel E. Acacio
Evaluating IA-32 web servers through simics: a practical experience. 251-264 - Tian Xia, Jien-Chung Lo:
On-chip short-time interval measurement system for high-speed signal timing characterization. 265-276 - Wei Zhang, Pepe Siy:
Comments on "Sign detection in residue arithmetic units" [Journal of Systems Architecture 45 (1998) 251-258]. 277-279
Volume 51, Number 5, May 2005
- Ali Karci
Generalized parallel divide and conquer on 3D mesh and torus. 281-295 - Montserrat Bóo, Margarita Amor:
High-performance architecture for anisotropic filtering. 297-314 - Matjaz Finc, Andrej Zemva:
Profiling soft-core processor applications for hardware/software partitioning. 315-329 - Shikun Zhou
Run-time analysis of time-critical systems. 331-345
Volume 51, Numbers 6-7, June-July 2005
- Henry Selvaraj, Lech Józwiak:
Reconfigurable embedded systems: Synthesis, design and application. 347-349 - Sebastian Wallner:
A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization. 350-367 - Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Distance-aware L2 cache organizations for scalable multiprocessor systems. 368-381 - Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj:
Multiple voltage and frequency scheduling for power minimization. 382-394 - Syed Saif Abrar:
Novel source-independent characterization methodology for embedded software energy estimation and optimization. 395-404 - Lech Józwiak, Szymon Bieganski, Artur Chojnacki:
Information-driven circuit synthesis with the pre-characterized gate libraries. 405-423 - Mariusz Rawski
An application of functional decomposition in ROM-based FSM implementation in FPGA devices. 424-434 - Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. 435-450
Volume 51, Number 8, August 2005
- Julio Sahuquillo
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. 451-469 - Arijit Bishnu, Bhargab B. Bhattacharya, Malay K. Kundu, C. A. Murthy, Tinku Acharya:
A pipeline architecture for computing the Euler number of a binary image. 470-487 - Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski:
Functional test generation based on word-level SAT. 488-511
Volume 51, Number 9, September 2005
- Lieven Eeckhout, Smaïl Niar, Koen De Bosschere:
Optimal sample length for efficient cache simulation. 513-525 - Lucia Lo Bello
A slot swapping protocol for time-critical internetworking. 526-541 - S. W. Ng, Edward Chan:
Equation-based TCP-friendly congestion control under lossy environment. 542-569
Volume 51, Numbers 10-11, October-November 2005
- Elizabeth Suet Hing Tse:
Switch fabric design for high performance IP routers: A survey. 571-601 - Sejin Park, Sang-Hwa Chung, Ben Lee:
Implementation and performance study of a hardware-VIA-based network adapter on Gigabit Ethernet. 602-616 - Ahmed Yassin Al-Dubai, Mohamed Ould-Khaoua, Lewis M. Mackenzie:
A plane-based broadcast algorithm for multicomputer networks. 617-632 - Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim:
Dynamic voltage scaling techniques for power efficient video decoding. 633-652 - Jun Yang, Jia Yu, Youtao Zhang:
A low energy cache design for multimedia applications exploiting set access locality. 653-664
Volume 51, Number 12, December 2005
- Péter Arató
Time-constrained scheduling of large pipelined datapaths. 665-687 - Fotios Gioulekas
Heterogeneous system level co-simulation for the design of telecommunication systems. 688-705
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