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Computer Architecture Letters, Volume 8
Volume 8, Number 1, January - June 2009
- Rohit Sunkam Ramanujam, Bill Lin:
Weighted Random Routing on Torus Networks. 1-4 - Jung Ho Ahn
, Jacob Leverich, Robert S. Schreiber, Norman P. Jouppi:
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs. 5-8 - Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang
A Predictive Shutdown Technique for GPU Shader Processors. 9-12 - Christopher Barnes, Pranav Vaidya, Jaehwan John Lee
An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators. 13-16 - Carlos Luque
CPU Accounting in CMP Processors. 17-20 - Vassos Soteriou
A High-Throughput Distributed Shared-Buffer NoC Router. 21-24 - Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. 25-28 - Aniruddha Desai, Jugdutt Singh:
Architecture Independent Characterization of Embedded Java Workloads. 29-32 - Elisardo Antelo
A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network". 33-34
Volume 8, Number 2, July - December 2009
- Jean-Luc Gaudiot:
Introducing the New Editor-in-Chief of IEEE Computer Architecture Letters. 37-38 - Kevin Skadron
Letter from the Editor. 39 - Jing Xin, Russ Joseph:
Exploiting Locality to Improve Circuit-Level Timing Speculation. 40-43 - Arvind Sudarsanam, Ramachandra Kallam, Aravind Dasu:
PRR-PRR Dynamic Relocation. 44-47 - Jacob Leverich, Matteo Monchiero, Vanish Talwar, Parthasarathy Ranganathan, Christos Kozyrakis:
Power Management of Datacenter Workloads Using Per-Core Power Gating. 48-51 - Enric Musoll:
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors. 52-55 - Alexandro Baldassin
Characterizing the Energy Consumption of Software Transactional Memory. 56-59 - James D. Balfour, R. C. Halting, William J. Dally:
Operand Registers and Explicit Operand Forwarding. 60-63 - Derek Chiou, Hari Angepat, Nikhil A. Patil, Dam Sunwoo:
Accurate Functional-First Multicore Simulators. 64-67
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