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IEEE Computer Architecture Letters, Volume 17

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Volume 17, Number 1, January - June 2018

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Alberto Scionti, Somnath Mazumdar, Stéphane Zuckerman:
Enabling Massive Multi-Threading with Fast Hashing. 1-4
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Dong-Ik Jeon, Kyeong-Bin Park, Ki-Seok Chung:
HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube. 5-8
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Sam Van den Steen, Lieven Eeckhout:
Modeling Superscalar Processor Memory-Level Parallelism. 9-12
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Srdjan Durkovic, Zoran Cica:
Birkhoff-Von Neumann Switch Based on Greedy Scheduling. 13-16
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Binh Pham, Derek Hower, Abhishek Bhattacharjee, Trey Cain:
TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches. 17-20
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Leonid Yavits, Ran Ginosar:
Accelerator for Sparse Machine Learning. 21-24
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Eleftherios-Iordanis Christoforidis, Sotirios Xydis, Dimitrios Soudris:
CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-Core Processors. 25-28
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Amjad F. Almatrood, Harpreet Singh:
Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata. 29-32
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Yue Zha, Jing Li:
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection. 33-36
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Myoungsoo Jung, Jie Zhang, Ahmed H. M. O. Abulila, Miryeong Kwon, Narges Shahidi, John Shalf, Nam Sung Kim, Mahmut T. Kandemir:
SimpleSSD: Modeling Solid State Drives for Holistic System Simulation. 37-41
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Zamshed I. Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew Lyle, Sachin S. Sapatnekar, Ulya R. Karpuzcu, Jianping Wang:
Efficient In-Memory Processing Using Spintronics. 42-46
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Mohammadamin Ajdari, Pyeongsu Park, Dongup Kwon, Joonsung Kim, Jangwoo Kim:
A Scalable HW-Based Inline Deduplication for SSD Arrays. 47-50
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Morteza Hoseinzadeh:
Flow-Based Simulation Methodology. 51-54
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Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Multi-Stage CPI Stacks. 55-58
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Guowei Zhang, Daniel Sánchez:
Leveraging Hardware Caches for Memoization. 59-63
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Armin Vakil-Ghahani, Sara Mahdizadeh-Shahri, Mohammad-Reza Lotfi-Namin, Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad:
Cache Replacement Policy Based on Expected Hit Count. 64-67
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Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides:
Sensing CPU Voltage Noise Through Electromagnetic Emanations. 68-71
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Daejin Jung, Sunjung Lee, Wonjong Rhee, Jung Ho Ahn:
Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping. 72-75
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Joshua San Miguel, Karthik Ganesan, Mario Badr, Natalie D. Enright Jerger:
The EH Model: Analytical Exploration of Energy-Harvesting Architectures. 76-79
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Jihun Kim, Joonsung Kim, Pyeongsu Park, Jong Kim, Jangwoo Kim:
SSD Performance Modeling Using Bottleneck Analysis. 80-83
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Kevin Angstadt, Jack Wadden, Vinh Dang, Ted Xie, Dan Kramp, Westley Weimer, Mircea Stan, Kevin Skadron:
MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem. 84-87
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Hao Zheng, Ahmed Louri:
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. 88-91
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Leila Delshadtehrani, Schuyler Eldridge, Sadullah Canakci, Manuel Egele, Ajay Joshi:
Nile: A Programmable Monitoring Coprocessor. 92-95
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Eojin Lee, Sukhan Lee, G. Edward Suh, Jung Ho Ahn:
TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering. 96-99

Volume 17, Number 2, July - December 2018

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Joydeep Rakshit, Kartik Mohanram:
LEO: Low Overhead Encryption ORAM for Non-Volatile Memories. 100-104
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Sang Wook Stephen Do, Michel Dubois:
Core Reliability: Leveraging Hardware Transactional Memory. 105-108
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Manolis Kaliorakis, Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos:
Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions. 109-112
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Soroosh Khoram, Yue Zha, Jing Li:
An Alternative Analytical Approach to Associative Processing. 113-116
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S. Karen Khatamifard, M. Hassan Najafi, Ali Ghoreyshi, Ulya R. Karpuzcu, David J. Lilja:
On Memory System Design for Stochastic Computing. 117-121
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Dimitris Mouris, Nektarios Georgios Tsoutsos, Michail Maniatakos:
TERMinator Suite: Benchmarking Privacy-Preserving Architectures. 122-125
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Esha Choukse, Mattan Erez, Alaa R. Alameldeen:
CompressPoints: An Evaluation Methodology for Compressed Memory Systems. 126-129
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Seikwon Kim, Wonsang Kwak, Changdae Kim, Jaehyuk Huh:
Zebra Refresh: Value Transformation for Zero-Aware DRAM Refresh Reduction. 130-133
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Youngeun Kwon, Minsoo Rhu:
A Case for Memory-Centric HPC System Architecture for Training Deep Neural Networks. 134-138
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Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang:
Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM. 139-142
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Konstantinos Iliakis, Sotirios Xydis, Dimitrios Soudris:
Decoupled MapReduce for Shared-Memory Multi-Core Architectures. 143-146
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Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Shaojun Wei:
Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. 147-150
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Engin Ipek, Florian Longnos, Shihai Xiao, Wei Yang:
Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM. 151-154
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Yu Gan, Christina Delimitrou:
The Architectural Implications of Cloud Microservices. 155-158
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Ofir Shwartz, Yitzhak Birk:
Distributed Memory Integrity Trees. 159-162
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Jitae Yun, Su-Kyung Yoon, Jeong-Geun Kim, Bernd Burgstaller, Shin-Dug Kim:
Regression Prefetcher with Preprocessing for DRAM-PCM Hybrid Main Memory. 163-166
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Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones:
RETROFIT: Fault-Aware Wear Leveling. 167-170
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Neeraj Kulkarni, Feng Qi, Christina Delimitrou:
Leveraging Approximation to Improve Datacenter Resource Efficiency. 171-174
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Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez:
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. 175-178
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Thiruvengadam Vijayaraghavan, Amit Rajesh, Karthikeyan Sankaralingam:
MPU-BWM: Accelerating Sequence Alignment. 179-182
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Sander De Pestel, Sam Van den Steen, Shoaib Akram, Lieven Eeckhout:
RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware. 183-186
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Wenyi Zhao, Quan Chen, Minyi Guo:
KSM: Online Application-Level Performance Slowdown Prediction for Spatial Multitasking GPGPU. 187-191
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Shivam Swami, Kartik Mohanram:
ARSENAL: Architecture for Secure Non-Volatile Memories. 192-196
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Abanti Basak, Xing Hu, Shuangchen Li, Sang Min Oh, Yuan Xie:
Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads. 197-200
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S. Karen Khatamifard, Longfei Wang, Selçuk Köse, Ulya R. Karpuzcu:
A New Class of Covert Channels Exploiting Power Management Vulnerabilities. 201-204
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Sushant Kondguli, Michael C. Huang:
Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance. 205-208
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Donald Kline Jr., Rami G. Melhem, Alex K. Jones:
Counter Advance for Reliable Encryption in Phase Change Memory. 209-212
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Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam:
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. 213-216
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Susumu Mashimo, Ryota Shioya, Koji Inoue:
VMOR: Microarchitectural Support for Operand Access in an Interpreter. 217-220
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Seungwon Min, Mohammad Alian, Wen-Mei Hwu, Nam Sung Kim:
Semi-Coherent DMA: An Alternative I/O Coherency Management for Embedded Systems. 221-224
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Negin Nematollahi, Mohammad Sadrosadati, Hajar Falahati, Marzieh Barkhordar, Hamid Sarbazi-Azad:
Neda: Supporting Direct Inter-Core Neighbor Data Exchange in GPUs. 225-229
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Hamza Omar, Halit Dogan, Brian Kahne, Omer Khan:
Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications. 230-234
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Farzaneh Zokaee, Hamid R. Zarandi, Lei Jiang:
AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs. 237-240
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Qian Lou, Lei Jiang:
BRAWL: A Spintronics-Based Portable Basecalling-in-Memory Architecture for Nanopore Genome Sequencing. 241-244
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Donghyun Min, DongGyu Park, Jinwoo Ahn, Ryan Walker, Junghee Lee, Sungyong Park, Youngjae Kim:
Amoeba: An Autonomous Backup and Recovery SSD for Ransomware Attack Defense. 245-248
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Chinam Kim, Hyukjun Lee:
A High-Bandwidth PCM-Based Memory System for Highly Available IP Routing Table Lookup. 246-249

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