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IEEE Computer Architecture Letters, Volume 11
Volume 11, Number 1, January - June 2012
- Simha Sethumadhavan, Ryan Roberts, Yannis P. Tsividis:
A Case for Hybrid Discrete-Continuous Architectures. 1-4 - Ji Kong, Peilin Liu, Yu Zhang:
Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs. 5-8 - Abhishek Deb, Josep M. Codina, Antonio González
:
A HW/SW Co-designed Programmable Functional Unit. 9-12 - Roberta Piscitelli, Andy D. Pimentel
A High-Level Power Model for MPSoC on FPGA. 13-16 - Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
An Overview of Static Pipelining. 17-20 - Lisa Wu
Cache Impacts of Datatype Acceleration. 21-24
Volume 11, Number 2, July - December 2012
- Nagesh B. Lakshminarayana, Jaekyu Lee
DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function. 33-36 - Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures. 37-40 - Reena Panda, Paul V. Gratz
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. 41-44 - Timothy N. Miller, Renji Thomas, Radu Teodorescu:
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units. 45-48 - Yang Li, Rami G. Melhem, Alex K. Jones
Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors. 49-52 - Christina Delimitrou, Sriram Sankar, Kushagra Vaid, Christos Kozyrakis:
Decoupling Datacenter Storage Studies from Access to Large-Scale Applications. 53-56 - Jie Chen, Guru Venkataramani, Gabriel Parmer:
The Need for Power Debugging in the Multi-Core Environment. 57-60 - Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, Parthasarathy Ranganathan:
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management. 61-64 - Tsahee Zidenberg, Isaac Keslassy
MultiAmdahl: How Should I Divide My Heterogenous Chip? 65-68
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