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ACM Transactions on Architecture and Code Optimization, Volume 20
Volume 20, Number 1, March 2023
- Thomas Luinaud
, J. M. Pierre Langlois
Symbolic Analysis for Data Plane Programs Specialization. 1:1-1:21 - Nilesh Rajendra Shah
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation. 2:1-2:28 - Mitali Soni
As-Is Approximate Computing. 3:1-3:26 - Parth Shah
TokenSmart: Distributed, Scalable Power Management in the Many-core Era. 4:1-4:26 - Zhangyu Chen
Lock-Free High-performance Hashing for Persistent Memory via PM-aware Holistic Optimization. 5:1-5:26 - Aristeidis Mastoras
Design and Implementation for Nonblocking Execution in GraphBLAS: Tradeoffs and Performance. 6:1-6:23 - Yemao Xu
SSD-SGD: Communication Sparsification for Distributed Deep Learning Training. 7:1-7:25 - Ataberk Olgun
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. 8:1-8:31 - Christos Sakalis
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. 9:1-9:24 - Yi Liang
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy. 10:1-10:25 - Suyeon Hur
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. 11:1-11:24 - Ashish Gondimalla
Occam: Optimal Data Reuse for Convolutional Neural Networks. 12:1-12:25 - Bo Peng
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations. 13:1-13:26 - Qiang Zhang
RegCPython: A Register-based Python Interpreter for Better Performance. 14:1-14:25 - Hai Jin
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V. 15:1-15:26 - Tuowen Zhao
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration. 16:1-16:26 - Manuela Schuler
XEngine: Optimal Tensor Rematerialization for Neural Networks in Heterogeneous Environments. 17:1-17:25 - Ivan Korostelev
YaConv: Convolution with Low Cache Footprint. 18:1-18:18 - Furkan Eris
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy. 19:1-19:25
Volume 20, Number 2, June 2023
- Nicolas Tollenaere
Autotuning Convolutions Is Easier Than You Think. 20:1-20:24 - Victor Perez, Lukas Sommer
User-driven Online Kernel Fusion for SYCL. 21:1-21:25 - Vinicius Espindola
Source Matching and Rewriting for MLIR Using String-Based Automata. 22:1-22:26 - Wenjing Ma
An Optimized Framework for Matrix Factorization on the New Sunway Many-core Platform. 23:1-23:24 - Sarabjeet Singh
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy. 24:1-24:20 - Chandra Sekhar Mummidi
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures. 25:1-25:19 - Qiaoyi Liu
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators. 26:1-26:26 - Ahmet Caner Yüzügüler
Scale-out Systolic Arrays. 27:1-27:25 - Francesco Minervini
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. 28:1-28:25 - Hadjer Benmeziane
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models. 29:1-29:21 - Dongwei Chen
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. 30:1-30:24 - Jingwen Du
Fast One-Sided RDMA-Based State Machine Replication for Disaggregated Memory. 31:1-31:25
Volume 20, Number 3, September 2023
- Abdul Rasheed Sahni
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes. 32:1-32:24 - Sooraj Puthoor
Turn-based Spatiotemporal Coherence for GPUs. 33:1-33:27 - Ruobing Chen
Jointly Optimizing Job Assignment and Resource Partitioning for Improving System Throughput in Cloud Datacenters. 34:1-34:24 - Gokul Subramanian Ravi
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency. 35:1-35:25 - Weizhi Xu
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs. 36:1-36:26 - Jin Zhao
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing. 37:1-37:24 - Yufeng Zhou
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead. 38:1-38:25 - Benjamin Reber
Cache Programming for Scientific Loops Using Leases. 39:1-39:25 - Xinfeng Xie
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing. 40:1-40:26 - Alexander Krolik
rNdN: Fast Query Compilation for NVIDIA GPUs. 41:1-41:25 - Jiazhi Jiang
Hierarchical Model Parallelism for Optimizing Inference on Many-core Processor via Decoupled 3D-CNN Structure. 42:1-42:21 - Yuwen Zhao
MFFT: A GPU Accelerated Highly Efficient Mixed-Precision Large-Scale FFT Framework. 43:1-43:23 - Muhammad Waqar Azhar
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. 44:1-44:25 - Dong Huang
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs. 45:1-45:26
Volume 20, Number 4, December 2023
- Jiangsu Du
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs. 46:1-46:22 - Hai Jin
A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures. 47:1-47:25 - Christian Menard
High-performance Deterministic Concurrency Using Lingua Franca. 48:1-48:29 - Donglei Wu
Smart-DNN+: A Memory-efficient Neural Networks Compression Framework for the Model Inference. 49:1-49:24 - Syed Salauddin Mohammad Tariq
MicroProf: Code-level Attribution of Unnecessary Data Transfer in Microservice Applications. 50:1-50:26 - Shiyi Li
gPPM: A Generalized Matrix Operation and Parallel Algorithm to Accelerate the Encoding/Decoding Process of Erasure Codes. 51:1-51:25 - Petros Anastasiadis
PARALiA: A Performance Aware Runtime for Auto-tuning Linear Algebra on Heterogeneous Systems. 52:1-52:25 - Hui Yu, Yu Zhang
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network. 53:1-53:26 - Victor Ferrari
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions. 54:1-54:26 - Bowen He
DxPU: Large-scale Disaggregated GPU Pools in the Datacenter. 55:1-55:23 - Shiqing Zhang
Characterizing Multi-Chip GPU Data Sharing. 56:1-56:24 - Jens Domke
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads. 57:1-57:26 - Satya Jaswanth Badri
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing. 58:1-58:25 - Miao Yu
Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator. 59:1-59:26 - Ziaul Choudhury
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. 60:1-60:25 - Zachary Susskind
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks. 61:1-61:24 - Jia Wei
Fastensor: Optimise the Tensor I/O Path from SSD to GPU for Deep Learning Training. 62:1-62:25
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