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33rd VLSI Design 2020: Bangalore, India
- 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020. IEEE 2020, ISBN 978-1-7281-5701-6
- Vishwani D. Agrawal:
Message from the Steering Committee Chair. i - David Atienza, Subhasish Mitra, Manan Suri:
Message from the Technical Program Co-Chairs. i - Amir Aminifar, Shabbir Batterywala:
Message from the Tutorial Co-Chairs. i - Sumit Goswami, Veeresh Shetty:
Message from the General Co-Chairs. i - Suk Lee:
Keynote: Technology directions for a bright semiconductor future. 1-8 - Abdelrahman Hosny, Andrew B. Kahng:
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update. 1-14 - Priyadarshini Panda, Kaushik Roy:
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems. 1-18 - Anuj Verma
, Rahul Shrestha:
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. 1-6 - Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti:
Power Efficient Sense Amplifier For Emerging Non Volatile Memories. 7-12 - Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. 13-18 - Ahish Shylendra, Sina Haji Alizad, Priyesh Shukla
Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS. 19-24 - Harita Sirugudi, Sharvani Gadgil
A Novel Low Power Ternary Multiplier Design using CNFETs. 25-30 - Mounika Kelam, Balaji Yadav Battu, Zia Abbas
3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications. 31-36 - Vinay Patil, Anuj Grover
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology. 37-42 - Elham Shamsa, Anil Kanduri, Nima Taherinejad, Alma Pröbstl, Samarjit Chakraborty
User-centric Resource Management for Embedded Multi-core Processors. 43-48 - Marcel Mettler
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. 49-54 - Srijit Dutta, Yaswanth Tavva, Debjyoti Bhattacharjee
Efficient Quantum Circuits for Square-Root and Inverse Square-Root. 55-60 - Prasad Kulkarni:
Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma Architecture. 61-66 - Sreeni Poolakkal, Nagarjuna Nallam:
Enhancing the Phase-Noise-Figure-of-Merit of a Resonator using Frequency Transformations. 67-71 - Satyajit Mohapatra, Nihar Ranjan Mohapatra:
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD). 72-77 - Frédéric Gessler, Philip Brisk, Mirjana Stojilovic
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. 78-83 - Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. 84-89 - Neelam Arya
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. 90-95 - Purnendu Bhattaru, Nagendra Krishnapura:
A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems. 96-100 - Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. 101-106 - Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde:
Analyzing Hardware Security Properties of Processors through Model Checking. 107-112 - Jitumani Sarma, Rakesh Biswas
VLSI based Adaptive Power Management Architecture for ECG Monitoring in WBAN. 113-118 - Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian:
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs. 119-124 - Srijeeta Maity, Anirban Ghose, Soumyajit Dey, Swarnendu Biswas:
Thermal Load-aware Adaptive Scheduling for Heterogeneous Platforms. 125-130 - Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar:
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. 131-136 - Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer:
Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs. 137-142 - Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment. 143-148 - Vishalini R. Laguduva, Shakil Mahmud, Sathyanarayanan N. Aakur, Robert Karam, Srinivas Katkoori
Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained Platforms. 149-154 - Nandan Kumar Jha, Rajat Saini, Subhrajit Nag, Sparsh Mittal:
E2GC: Energy-efficient Group Convolution in Deep Neural Networks. 155-160 - Prudhvi Raj Thota, Kiran Wadagavi, Namani Rakesh, Sumit Bhat, Abirmoya Santra:
A Low Noise, Low Power, Wide Range Programmable Output Reference Buffer for Sensor Applications. 161-164 - Venkatesh Kadlimatti, Prudhvi Raj Thota, Sumit Bhat:
A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display Applications. 165-170 - Yasaswy Kasarabada, Ranga Vemuri
StateLock: State Transition Based Logic Locking for Sequential Circuits. 171-176 - Joydeep Kumar Devnath, Neelam Surana, Joycee Mekie:
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks. 177-182 - K. A. Shahan, J. Sheeba Rani:
FPGA based convolution and memory architecture for Convolutional Neural Network. 183-188 - Md Toufiq Hasan Anik, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi:
On the Effect of Aging on Digital Sensors. 189-194 - Arjun Singh Chauhan, Vineet Sahula, A. S. Mandal, Abhigyan Dutta:
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation. 195-200 - Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen:
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling. 201-206 - Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar:
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. 207-212 - Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal:
A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design Issues. 213-218 - Amit Patil, Sumit Bhat, Abirmoya Santra:
An Accurate, Power and Area Efficient 13.33x Charge Pump with Wide-Range Programmability for Biomedical Sensors. 219-224
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