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VTS 2007: Berkeley, CA, USA
- 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA. IEEE Computer Society 2007, ISBN 0-7695-2812-0
RF Test I
- Erkan Acar, Sule Ozev, Kevin B. Redmond:
A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up. 3-8 - Haralampos-G. D. Stratigopoulos, Petros Drineas
, Mustapha Slamani, Yiorgos Makris
Non-RF to RF Test Correlation Using Learning Machines: A Case Study. 9-14 - Marcelo Negreiros
RF Digital Signal Generation Beyond Nyquist. 15-22
Delay Test Quality
- Soumitra Bose, Vishwani D. Agrawal:
Delay Test Quality Evaluation Using Bounded Gate Delays. 23-28 - Bram Kruseman, Ananta K. Majhi, Guido Gronthoud:
On Performance Testing with Path Delay Patterns. 29-34 - K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits. 35-42
Memory Test
- Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. 47-52 - Yu-Tsao Hsing
SDRAM Delay Fault Modeling and Performance Testing. 53-58 - Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
Optimizing Test Length for Soft Faults in DRAM Devices. 59-66
Test Compression
- Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini:
Minimizing the Impact of Scan Compression. 67-74 - Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Embedded Deterministic Test. 75-83 - Anshuman Chandra, Haihua Yan, Rohit Kapur:
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. 84-92
Going after Defects
- Claude Thibeault:
On a New Outlier Rejection Technique. 97-103 - Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee:
Enhanced Resolution Jitter Testing Using Jitter Expansion. 104-109 - Hsiang-Hui Huang, Ching-Hwa Cheng:
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. 110-118
Online Test
- Amit Laknaur, Rui Xiao, Haibo Wang:
A Programmable Window Comparator for Analog Online Testing. 119-124 - Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee:
Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. 125-130 - Xiaojun Ma, Jing Huang, Fabrizio Lombardi:
Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets. 131-140
Diagnosis I
- Daniel Arumí
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. 145-150 - Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou:
Handling Pattern-Dependent Delay Faults in Diagnosis. 151-157 - Rosa Rodríguez-Montañés, Daniel Arumí
Diagnosis of Full Open Defects in Interconnecting Lines. 158-166
ATPG for Delay Faults
- V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. 167-172 - Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland:
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. 173-178 - Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
Supply Voltage Noise Aware ATPG for Transition Delay Faults. 179-186
Advances in Test
- Kyoung Youn Cho, Edward J. McCluskey:
Test Set Reordering Using the Gate Exhaustive Test Metric. 199-204 - Jennifer Dworak:
An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting. 205-210 - Richard Putman, Nur A. Touba:
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. 211-218
Diagnosis II
- Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
Accelerating Diagnosis via Dominance Relations between Sets of Faults. 219-224 - Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. 225-230 - Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. 231-238
Failure Estimation
- Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs. 243-248 - John P. Hayes, Ilia Polian, Bernd Becker
An Analysis Framework for Transient-Error Tolerance. 249-255 - Brian Mullins, Hossein Asadi
Case Study: Soft Error Rate Analysis in Storage Systems. 256-264
Fault Prediction & Evaluation
- Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware:
Silicon Evaluation of Static Alternative Fault Models. 265-270 - Simon P. Wilson
Parameter Estimation for a Model with Both Imperfect Test and Repair. 271-276 - Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra:
Circuit Failure Prediction and Its Application to Transistor Aging. 277-286
Analog Test
- Byoungho Kim, Zhenhai Fu, Jacob A. Abraham:
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. 291-296 - Vishwanath Natarajan, Ganesh Srinivasan, Abhijit Chatterjee, Craig Force:
Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios. 297-302 - Le Jin, Degang Chen, Randall L. Geiger:
Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal. 303-310
High Level Test Techniques
- Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour
High Level Synthesis of Degradable ASICs Using Virtual Binding. 311-317 - Jian Kang, Sharad C. Seth, Vijay Gangaram:
Efficient RTL Coverage Metric for Functional Test Selection. 318-324 - Kedarnath J. Balakrishnan, Lei Fang:
RTL Test Point Insertion to Reduce Delay Test Volume. 325-332
Memory Repair
- Avijit Dutta, Nur A. Touba:
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. 349-354 - Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen:
A Built-In Self-Repair Scheme for Multiport RAMs. 355-360 - Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. 361-368
SOC Test
- Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. 369-374 - Jaehoon Song, Piljae Min, Hyunbean Yi, Sungju Park:
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip. 375-380 - Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test. 381-388
RF Test II
- T.-L. Hung, J.-L. Huang:
A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing. 389-394 - Rajarajan Senguttuvan, Abhijit Chatterjee:
Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection. 395-400 - Yen-Chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu:
A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications. 401-408
Design for Test
- Peter Wohl, John A. Waicukauski, Sanjay Patel:
Automated Design and Insertion of Optimal One-Hot Bus Encoders. 409-415 - Irith Pomeranz, Sudhakar M. Reddy:
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. 416-421 - Hafizur Rahaman
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). 422-430
Testing Large Chips
- Alexandre M. Amory
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. 435-440 - Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors. 441-446 - Matthieu Tuna, Mounir Benabdenbi, Alain Greiner:
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. 447-454
Ensuring Secure Chips
- Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. 455-460 - Chunsheng Liu, Yu Huang:
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. 461-468
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