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34th SoCC 2021: Las Vegas, NV, USA
- Gang Qu, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar:
34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021. IEEE 2021, ISBN 978-1-6654-2931-3 - Gongbo Chen, Giray Atabey Kirtiz, Christian Wiede, Rainer Kokozinski:
Implementation and Evaluation of a Neural Network-Based LiDAR Histogram Processing Method on FPGA. 1-6 - Mahesh M, Nalesh S, S. Kala:
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. 7-12 - Mohammadreza Baharani
, Ushma Sunil Bharucha, Kaustubh Manohar Mhatre, Hamed Tabkhi:
Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAs. 13-18 - Naveed Mahmud, Andrew MacGillivray, Manu Chaudhary, Esam El-Araby:
Optimizing Quantum Circuits for Arbitrary State Synthesis and Initialization. 19-24 - Anil Kumar Gundu, Volkan Kursun:
Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology. 25-28 - Hugo D. Hernandez, Diego Augusto Pontes, Bruno Soares, Dionisio de Carvalho
Dual-Band GSM Energy Harvester for a Duty-Cycle Approach in 180nm CMOS Technology. 29-33 - Xuan Viet Linh Nguyen, Tony Gerges
Stereolithography-Based Rectenna for Wireless Energy Harvesting. 34-39 - Lukas Jünger, Alexander Belke, Rainer Leupers:
Software-defined Temporal Decoupling in Virtual Platforms. 40-45 - Antoine Gautier, Benoît Larras, Olev Märtens, Deepu John
Embedded ICG-based Stroke Volume Measurement System: Comparison of Discrete-Time and Continuous-Time Architectures. 46-51 - Puyang Zheng, Xiao Sha
Analysis of the Sub-µA Fully Integrated NMOS LDO for Backscattering System. 52-56 - Shahram Hatefi Hesari, Nicole McFarlane:
A SiPM Based Sensor For Nuclear Detection Applications. 57-62 - Prokash Ghosh
A Design Approach to Reduce Test Time on SOC Memories. 63-66 - Jaya Dofe, Wafi Danesh:
LC-Physical Unclonable Function in Wireless 3D IC for Securing Internet of Things Devices. 67-70 - David Akselrod:
Reinforcement Learning-based Power Management Architecture for Optimal DVFS in SoCs. 71-74 - Rodrigue Rizk
An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations. 75-78 - Dominick Rizk
A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function. 79-82 - Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Jürgen Becker:
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips. 83-88 - Süleyman Savas, Endri Bezati, Jörn W. Janneck:
Generating hardware and software for RISC-V cores generated with Rocket Chip generator. 89-94 - Tibor Gergely Markovits, Péter Arató, György Rácz:
Implementation of an SoC architecture with built-in safety features. 95-100 - Abhijitt Dhavlle, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao:
Power Swapper: Approximate Functional Block Assisted Cryptosystem Security. 101-105 - Aditya Kulkarni, Ayush Singh, Sachin Arun Waje, Sunil Shrirangrao Kashide, Seonil Brian Choi:
TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs. 106-111 - Viswanath G. Akkili, Viranjay M. Srivastava
Performance Optimization of p-Channel SnO Cylindrical Thin Film Transistors (CTFT) Using 3D Modelling. 112-116 - Xiao Sha
1.81 kHz Relaxation Oscillator With Forward Bias Comparator and Leakage Current Compensation Based Techniques. 117-122 - Richard Gebauer
Taskrunner: A Flexible Framework Optimized for Low Latency Quantum Computing Experiments. 123-128 - Junqi Wang, Yida Li, Qing Liu, Huizhang Luo, Kenli Li:
Total Variation Reduction for Lossless Compression of HPC Applications. 129-134 - Kang Liu, Jeff Jun Zhang, Benjamin Tan, Dan Feng:
Can We Trust Machine Learning for Electronic Design Automation? 135-140 - Dawei Li, Cong Liu, Xiaowei Xu:
Efficient Localization of Origins of PVC based on Random Signal Segmentation. 141-145 - Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
On Reduction of Computations for Threshold Function Identification. 146-151 - Che-Hao Chang, Chih-Tsun Huang:
Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator. 152-157 - Zhuoyu Chen, Pingcheng Dong, Zhuoao Li, Ruoheng Yao, Yunhao Ma
Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm. 158-163 - Surbhi Chhabra
Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core. 164-169 - Lingjuan Wu, Xuefei Li, Jiacheng Zhu, Jian Zheng, Wei Hu:
Identifying Specious LUTs for Satisfiability Don't Care Trojan Detection. 170-175 - Jeff Anderson, Yousra Alkabani, Tarek A. El-Ghazawi:
ReCPE: A PE for Reconfigurable Lightweight Cryptography. 176-181 - Bo Bao, Jason Anderson:
Dynamic Power Analysis of Standard-Cell FPGA Fabrics. 182-187 - Prokash Ghosh
A Framework for Evaluation of Debug Path Performance in SoC. 188-193 - Aniruddha Roy, Khyati Bansal, Nitin Agarwal:
On the stability, transient and quiescent current control of one low-voltage class-AB op-amp architecture. 194-199 - Samuel Ellicott, Michael Kines, Waleed Khalil, Yu Qi
Analog-Inspired Hardware Security: A Low-Energy Solution for IoT Trusted Communications. 200-205 - Rabin Yu Acharya, Michael Valentin Levin, Domenic Forte
LDO-based Odometer to Combat IC Recycling. 206-211 - Xingye Liu, Paul Ampadu:
Distributed On-Chip Power Supply for Security Enhancement in Multicore NoC. 212-217 - Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang:
A Two-Stage Path Planning Engine for Robot Navigation System. 218-223 - Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An IMU-aided Fitness System. 224-229 - Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Cluster Tool Performance Analysis using Graph Database. 230-235 - Melvin Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, Sander Stuijk
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators. 236-241 - Peter Gadfort, Oluseyi A. Ayorinde:
FPNA: A Reconfigurable Accelerator for AI Inference at the Edge. 242-247 - Nidhi Anantharajaiah, Felix Knopf, Jürgen Becker:
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems. 248-253 - Arnab A. Purkayastha, Hamed Tabkhi:
Design Study on Impact of Memory Access Parallelism for Cloud FPGAs. 254-259 - Soner Seçkiner, Selçuk Köse:
Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation. 260-265 - Kun-Chih Jimmy Chen
A Convolutional Neural Network on Chip Design Methodology for CNN Hardware Implementation. 266-271 - Yung-Yu Tsai, Jin-Fu Li:
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults. 272-277 - Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou:
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. 278-283
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