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SiPS 2014: Belfast, United Kingdom
- 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014. IEEE 2014, ISBN 978-14799-6588-5
Synthesis & Optimisation
- Ilya Chukhman, Shuvra S. Bhattacharyya
:
Instrumentation-driven framework for validation of dataflow applications. 1-6 - Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck:
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 7-12 - Jörn Schumacher
High-performance sparse fast Fourier transforms. 13-18
Image Processing Architectures
- Nanoka Sumi
Effect of computation offload on performance and energy consumption of mobile face recognition. 19-25 - Fahad Manzoor Siddiqui
IPPro: FPGA based image processing processor. 26-31 - Junlin Chen, Lei Wang:
Energy-adaptive performance management for self-sustained signal processing systems. 32-37 - Erwan Nogues, Simon Holmbacka, Maxime Pelcat, Daniel Ménard, Johan Lilius
Power-aware HEVC decoding with tunable image quality. 38-43
Arithmetic
- Injae Yoo, In-Cheol Park
A search-less DEC BCH decoder for low-complexity fault-tolerant systems. 44-49 - Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre
Computation-skip error resilient scheme for recursive CORDIC. 50-55 - Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A reduced latency list decoding algorithm for polar codes. 56-61 - Ciara Moore
Accelerating integer-based fully homomorphic encryption using Comba multiplication. 62-67
Posters I
- Farhana Sheikh
Channel-adaptive complex K-best MIMO detection using lattice reduction. 68-73 - Flávio S. Brás, Filipe E. Ferreira, Francisco A. Monteiro
Interference suppression with physical-layer network coding and MIMO for multi-way channels. 74-79 - Zeyuan Li, Pei-Jung Chung:
Weighted least squares solution for RSS based localization in correlated shadowing. 80-84 - Siyuan Wei, Ming Yang, Chaitali Chakrabarti, Richard Sampson, Thomas F. Wenisch, Oliver Kripfgans
A low complexity scheme for accurate 3D velocity estimation in ultrasound systems. 85-90 - Runle Du, Jiaqi Liu, Zhifeng Li, Zhenhong Niu, Zhiye Jiang, Yadong Yang:
Composite data fusion algorithm for miniature vehicles building navigation base in formation flying. 91-96 - Laurent Cabaret
What is the world's fastest connected component labeling algorithm? 97-102 - Asma Qureshi, Maïté Brandt-Pearce
On modified EMD: Selective extrema analysis. 103-108
Special Session: Application-Specific Instruction Set Processors
- Janne Janhunen, Pekka Jääskeläinen
Programmable in-loop deblock filter processor for video decoders. 109-114 - Julian Hartig, Lukas Gerlach
Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices. 115-120 - Yun Wu
FPGA-based Tabu search for detection in large-scale MIMO systems. 121-126 - Heikki Kultala
Compiler optimizations for code density of variable length instructions. 127-132
Memory Architectures
- Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross:
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. 133-138 - Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao
Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. 139-144 - Shigui Qi, Dan Feng, Jingning Liu:
Optimal voltage signal sensing of NAND flash memory for LDPC code. 145-150 - Dong-hwan Lee, Wonyong Sung:
Direct and indirect measurement of inter-cell capacitance in NAND flash memory. 151-156
Foundations
- Lachlan J. Gunn
Real-time compensation of static distortion by measurement of differential noise gain. 157-161 - Pei-Wen Huang, Wei-Jung Jou, Yu-Min Lin, Hsiao-I Jen, Sung-Chun Tang
Trend-extracted MSE based on adaptive aligned EEMD with early termination scheme: Analysis of the acute stroke patients' physiological signals. 162-167 - Ryan M. Corey
A low complexity estimation architecture based on noisy comparators. 168-173 - Kyuyeon Hwang
Fixed-point feedforward deep neural network design using weights +1, 0, and -1. 174-179
Communications Architectures
- Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Software polar decoder on an embedded processor. 180-185 - Li-Hong Huang, Kai-Ting Shr, Ming-Hung Lin, Yuan-Hao Huang:
Design and implementation of a convex-optimized positioning system on wireless RF/FPGA platform. 186-191 - Farhana Sheikh
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. 192-197 - Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Symbol-based successive cancellation list decoder for polar codes. 198-203
Posters II
- Michal Stala, Ove Edfors
Implementation of a novel architecture for DFT-based channel estimators in OFDM systems. 204-209 - Chris Ceroici, Vincent C. Gaudet
FPGA implementation of a clockless stochastic LDPC decoder. 210-214 - Gabi Sarkis, Pascal Giard, Alexander Vardy
Increasing the speed of polar list decoders. 215-220 - Chi Wen Cheng, Yu Sheng Lin, Shao-Yi Chien
Efficient reconfigurable architecture for MIMD streaming execution using permutation network. 221-225 - Neil Hanley, Máire O'Neill, Michael Tunstall
Empirical evaluation of multi-device profiling side-channel attacks. 226-231 - Mona Aghababaeetafreshi
IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor. 232-237 - Colm Kelly, Fahad Manzoor Siddiqui
Histogram of oriented gradients front end processing: An FPGA based processor approach. 238-243
Special Session: Acceleration & Optimisation for Visual Signal Processing
- Chun-Fu Chen, Gwo Giun Chris Lee, Zheng-Han Yu, Chun-Hsi Huang:
Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration. 244-249 - Tse-Wei Chen, Noriyasu Hashiguchi, Masahiro Ariizumi, Kinya Osa, Daisuke Nakashima, Yasuo Fukuda, Shiori Wakino, Shinji Shiraga, Masami Kato:
Acceleration of clustering-based superpixel algorithms with low memory costs. 250-255 - Amr Suleiman, Vivienne Sze:
Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support. 256-261 - Wei-Kai Chan, Yu-Hsiang Tseng, Yu-Sheng Lin, Shao-Yi Chien
Coarse-grained reconfigurable stream processor for distributed smart cameras. 262-267
Special Session: Hardware Accelerators for Visual Analytics
- Qinru Qiu, Zhe Li, Khadeer Ahmed, Hai (Helen) Li
Neuromorphic acceleration for context aware text image recognition. 268-273 - Francesco Conti
Energy-efficient vision on the PULP platform for ultra-low power parallel computing. 274-279 - Nandhini Chandramoorthy, Karthik Swaminathan, Matthew Cotter, Xueqing Li, Indranil Palit, Xiaobo Sharon Hu
Understanding the landscape of accelerators for vision. 280-285 - Brandon B. Jennings, Reggie Barnett, Chet N. Gnegy, John A. Carpenter, Yan Fang, Donald M. Chiarulli, Steven P. Levitan:
HMAX image processing pipeline with coupled oscillator acceleration. 286-291
Special Session: Dataflow Modelling & Synthesis
- Adnan Bouakaz, Thierry Gautier, Jean-Pierre Talpin:
Earliest-deadline first scheduling of multiple independent dataflow graphs. 292-297 - Jonathan Piat, Jérémie Crenne:
Modeling dynamic partial reconfiguration in the dataflow paradigm. 298-303 - Francesca Palumbo
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy. 304-309 - Erwan Nogues, Daniel Ménard:
Efficient fixed-point refinement of DSP dataflow systems. 310-315
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