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SBCCI 2012: Brasilia, Brazil
- 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasilia, Brazil, August 30 - September 2, 2012. IEEE 2012, ISBN 978-1-4673-2606-3
- Johanna Sepúlveda, Guy Gogniat
, Ricardo Pires, Jiang Chau Wang, Marius Strum:
Hybrid-on-chip communication architecture for dynamic MP-SoC protection. 1-6 - Ygo N. Batista, Cristiano C. de Araújo, Abel G. Silva-Filho:
FPGA design for real time flaw detection on edges using the LEDges technique. 1-6 - Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura:
Application-Specific Network-on-Chip synthesis with topology-aware floorplanning. 1-6 - Frank Sill Torres, Rodrigo Possamai Bastos:
Robust modular Bulk Built-in Current Sensors for detection of transient faults. 1-6 - Zubair Wadood Bhatti, Narasinga Rao Miniskar
Memory and communication driven spatio-temporal scheduling on MPSoCs. 1-6 - Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Design-oriented delay model for CMOS inverter. 1-6 - Carlos Augusto de Moraes Cruz, Israel L. Marinho, Davies William de Lima Monteiro
Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response. 1-6 - Zia Abbas
Yield optimization for low power current controlled current conveyor. 1-6 - Cecil Accetti R. de A. Melo
FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance Systems. 1-5 - Henrique Luiz Andrade Pimentel, Sergio Bampi:
A 50MHz-lGHz wideband low noise amplifier in 130nm CMOS technology. 1-6 - Thiago R. da Rosa, Vivian Larrea, Ney Calazans, Fernando Gehm Moraes
Power consumption reduction in MPSoCs through DFS. 1-6 - Paulo Sérgio B. do Nascimento, Francisco A. S. Neves
FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector. 1-6 - Yuri Gonzaga Gonçalves da Costa, José Antônio Gomes de Lima, Guilherme Navarro:
A low complexity lossless data compressor IP-core for satellite images. 1-6 - Hugo Daniel Hernández
DPA insensitive voltage regulator for contact smart cards. 1-4 - Abdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz:
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. 1-6 - Jefferson Daniel de Barros Soldera, Julio Cesar Saldana, Cesar Giacomini Penteado, Hugo Daniel Hernández
On-chip 4to20mA reconfigurable current loop transmitter for smart sensor applications. 1-6 - Cristiano Santos, Ricardo Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte:
Multi-bit flip-flop usage impact on physical synthesis. 1-6 - Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Partitioning-based wirelength estimation technique for Y-routing. 1-6 - Edgar Mauricio Camacho-Galeano, Alfredo Olmos, Andre Vilas Boas:
A very low power area efficient CMOS only bandgap reference. 1-6 - Fernanda D. V. R. Oliveira, Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Current-mode analog integrated circuit for focal-plane image compression. 1-6 - Yan Ghidini, Thais Webber
Topological impact on latency and throughput: 2D versus 3D NoC comparison. 1-6 - Everson Martins, Matheus A. Alejandro, Thais V. Fogaca:
Differential mixer with NMOS/PMOS stack at switching stage. 1-3 - Ricardo Vanni Dallasen, Gilson Inácio Wirth
A PLL for clock generation with automatic frequency control under TID effects. 1-5 - Jefferson B. D. Soldera, Michael Todd Berens, Alfredo Olmos:
A temperature compensated CMOS relaxation oscillator for low power applications. 1-4 - João Bispo
Hardware pipelining of runtime-detected loops. 1-6 - Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. 1-6 - Omer Malik, Ahmed Hemani:
A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture. 1-6 - Fabiane Rediess, Luciano Volcan Agostini
High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding. 1-5 - Renato Coral Sampaio
Hardware and software co-design for the AAC audio decoder. 1-6 - Heiner Alarcon Cubas, Joao Navarro Soares Jr.:
Top-down design for Low power Multi-bit Sigma-Delta Modulator. 1-6 - Thiago N. C. Cardoso, Edna Barros, Bruno O. Prado, Andre Aziz:
Communication software synthesis from UML-ESL models. 1-6 - Seyed-Hosein Attarzadeh-Niaki, Gilmar S. Beserra, Nikolaj Andersen, Mathias Verdon, Ingo Sander:
Heterogeneous system-level modeling for small and medium enterprises. 1-6 - Sophie Drean, Nathalie Deltimple, Eric Kerherve, Baudouin Martineau, Didier Belot:
A 65nm CMOS 60 GHz class F-E power amplifier for WPAN applications. 1-4 - Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. 1-6 - Jones Yudi Mori, Carlos H. Llanos
Kernel analysis for architecture design trade off in convolution-based image filtering. 1-6
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