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ISPD 2012: Napa, California, USA
- Jiang Hu, Cheng-Kok Koh:
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012. ACM 2012, ISBN 978-1-4503-1167-0
Welcome and keynote address
- Burn J. Lin:
Lithography till the end of Moore's law. 1-2
Advanced processess
- Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Design-aware lithography. 3-8 - Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
:
Graph-based subfield scheduling for electron-beam photomask fabrication. 9-16 - Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong
A polynomial time exact algorithm for self-aligned double patterning layout decomposition. 17-24 - Jhih-Rong Gao, David Z. Pan:
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. 25-32
Emerging challenges and technologies
- Kwang-Ting (Tim) Cheng
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications. 33-40 - Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He:
A fast estimation of SRAM failure rate using probability collectives. 41-48 - Tsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho
Integrated fluidic-chip co-design methodology for digital microfluidic biochips. 49-56
Commemoration for Professor C.-L. Liu
- Jason Cong:
Transformation from ad hoc EDA to algorithmic EDA. 57-62 - Martin D. F. Wong
On simulated annealing in EDA. 63-64 - Tong Gao, Prashant Saxena:
On pioneering nanometer-era routing problems. 65-68 - C. L. Liu:
I attended the nineteenth design automation conference. 69-70
Analog, datapath, and detailed placement
- Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang:
Routability-driven placement algorithm for analog integrated circuits. 71-78 - Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. 79-86 - Shuai Li, Cheng-Kok Koh:
Mixed integer programming models for detailed placement. 87-94
Power and thermal modeling and optimization
- Alexander Korobkov:
Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs). 95-96 - Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu
Efficient on-line module-level wake-up scheduling for high performance multi-module designs. 97-104 - Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng:
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. 105-112 - Bing Shi, Ankur Srivastava
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs. 113-118
Clocking and routing
- Venky Ramachandran:
Construction of minimal functional skew clock trees. 119-120 - Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen:
Novel pulsed-latch replacement based on time borrowing and spiral clustering. 121-128 - Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen:
On construction low power and robust clock tree via slew budgeting. 129-136 - Wen-Hao Liu, Yih-Lang Li:
Optimizing the antenna area and separators in layer assignment of multi-layer global routing. 137-144
Gate sizing
- Gregory Shklover, Ben Emanuel:
Simultaneous clock and data gate sizing algorithm with common global objective. 145-152 - Andrew B. Kahng, Seokhyeong Kang:
Construction of realistic gate sizing benchmarks with known optimal solutions. 153-160 - Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo:
The ISPD-2012 discrete cell sizing contest and benchmark suite. 161-164
Congestion-driven logic and physical synthesis
- Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar:
Towards layout-friendly high-level synthesis. 165-172 - Janet L. Olson:
Synthesis for advanced nodes: an industry perspective. 173-174 - Patrick Groeneveld:
Reality-driven physical synthesis. 175-178
Floorplanning and mixed-size placement
- Jackey Z. Yan, Chris Chu:
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. 179-186 - Renshen Wang, Nimish Shah:
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip. 187-192 - Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji:
MAPLE: multilevel adaptive placement for mixed-size designs. 193-200 - Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
A size scaling approach for mixed-size placement. 201-206
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