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ISPD 2008: Portland, Oregon, USA
- David Z. Pan, Gi-Joon Nam:
Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008. ACM 2008, ISBN 978-1-60558-048-7
Keynote address
- Antun Domic:
Design or manufacturing: which will be best for the future of the semiconductor roadmap? 1
Physical optimization techniques with buffering and gate sizing
- David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. 2-9 - Jason Cong, John Lee, Lieven Vandenberghe:
Robust gate sizing via mean excess delay minimization. 10-14 - Yifang Liu, Jiang Hu, Weiping Shi:
Multi-scenario buffer insertion in multi-core processor designs. 15-22 - Bruce Tseng, Hung-Ming Chen:
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. 23-30
Advances in placement
- Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
:
Metal-density driven placement for cmp variation and routability. 31-38 - Jason Cong, Guojie Luo:
Highly efficient gradient computation for density-constrained analytical placement methods. 39-46 - Peter Spindler, Ulf Schlichtmann
Abacus: fast legalization of standard cell circuits with minimal movement. 47-53 - Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences. 54-59
Statistical and physical design for manufacturability -- act II
- Patrick McGuinness:
Variations, margins, and statistics. 60-67 - Ed Grochowski, Murali Annavaram
Implications of device timing variability on full chip timing. 68 - Andrew B. Kahng:
How to get real mad. 69 - Phiroze N. Parakh, Shankar Krishnamoorthy:
A robust approach to lithography friendly design implementation. 70
Interconnect synthesis and structured ASIC
- Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment. 71-77 - M.-C. Frank Chang
RF interconnects for communications on-chip. 78-83 - Herman Schmit, Amit Gupta, Radu Ciobanu:
Placement challenges for structured ASICs. 84-86
Logic optimizations for physical synthesis
- Hosung (Leo) Kim, John Lillis:
A framework for layout-level logic restructuring. 87-94 - Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Optimizing non-monotonic interconnect using functional simulation and logic restructuring. 95-102 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Reap what you sow: spare cells for post-silicon metal fix. 103-110
Advances in routing
- Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion. 111-117 - Chih-Hung Liu
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree. 118-125 - Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. 126-133 - Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng:
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. 134-141
Modern global routing issues and ISPD-08 global routing contest
- William Swartz:
Issues in global routing. 142-147 - Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov:
The coming of age of (academic) global routing. 148-155 - Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz:
The ISPD global routing benchmark suite. 156-159
Electrical issues and clock network design in physical synthesis
- Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. 160-167 - Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Stress aware layout optimization. 168-174 - Rupak Samanta, Jiang Hu, Peng Li:
Discrete buffer and wire sizing for link-based non-tree clock networks. 175-181 - Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design. 182-189
Physical design for bio-microfluidics
- Tao Xu, Krishnendu Chakrabarty
Automated design of digital microfluidic lab-on-chip under pin-count constraints. 190-198 - Tamal Mukherjee
Physical design issues in biofluidic microchips. 199 - Minsik Cho, David Z. Pan:
A high-performance droplet router for digital microfluidic biochips. 200-206
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