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ISPD 2005: San Francisco, California, USA
- Patrick Groeneveld, Louis Scheffer:
Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005. ACM 2005, ISBN 1-59593-021-3 - Rajeev Madhavan:
The death of logic synthesis. 1
Routing techniques
- Robert F. Lembach, Rafael A. Arce-Nazario
, Donald Eisenmenger, Cory Wood:
A diagnostic method for detecting and assessing the impact of physical design optimizations on routing. 2-6 - Jin-Yih Li, Yih-Lang Li:
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. 7-13 - Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten:
Routing of analog busses with parasitic symmetry. 14-19 - Di Wu, Jiang Hu, Rabi N. Mahapatra:
Coupling aware timing optimization and antenna avoidance in layer assignment. 20-27 - Chris C. N. Chu, Yiu-Chung Wong:
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. 28-35 - Yukiko Kubo, Atsushi Takahashi
A global routing method for 2-layer ball grid array packages. 36-43
Geometric programming and clocks
- Stephen P. Boyd, Seung-Jean Kim:
Geometric programming for circuit optimization. 44-46 - Baris Taskin, Ivan S. Kourtev:
Delay insertion method in clock skew scheduling. 47-54 - Anand Rajaram, David Z. Pan, Jiang Hu:
Improved algorithms for link-based non-tree clock networks for skew variability reduction. 55-62
Power, buffering and open source
- Atsushi Muramatsu, Masanori Hashimoto
Effects of on-chip inductance on power distribution grid. 63-69 - Jaskirat Singh, Sachin S. Sapatnekar:
A fast algorithm for power grid design. 70-77 - Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. 78-85 - Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm. 86-93 - Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov:
Early research experience with OpenAccess gear: an open source development environment for physical design. 94-100 - Gary Smith:
A new era for CAD. 101
Keynote and tutorial on the history and future of physical design
- Jue-Hsien Chern:
Challenges of analog/mixed-signal SoC design and verification. 102 - Andrzej J. Strojwas:
Tutorial on DFM for physical design. 103
Floorplanning
- Tung-Chieh Chen, Yao-Wen Chang:
Modern floorplanning based on fast simulated annealing. 104-112 - Jill H. Y. Law, Evangeline F. Y. Young:
Multi-bend bus driven floorplanning. 113-120 - Mario R. Casu, Luca Macchiarulo:
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. 121-128 - Hayward H. Chan, Saurabh N. Adya, Igor L. Markov:
Are floorplan representations important in digital design? 129-136
Technology mapping
- Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar:
An efficient technology mapping algorithm targeting routing congestion under delay constraints. 137-144 - Qinghua Liu, Malgorzata Marek-Sadowska:
Wire length prediction-based technology mapping and fanout optimization. 145-151 - I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim
Mapping algorithm for large-scale field programmable analog array. 152-158
Advanced techniques and technologies
- James D. Z. Ma, Rob A. Rutenbar
Fast interval-valued statistical interconnect modeling and reduction. 159-166 - Brent Goplen, Sachin S. Sapatnekar:
Thermal via placement in 3D ICs. 167-174 - Xin Yuan, Kevin W. McCullen
Technology migration technique for designs with strong RET-driven layout restrictions. 175-182
Physical synthesis
- Shankar Krishnamoorthy:
Insights and perspectives on physical synthesis. 183 - Paul Villarrubia:
Physical design tools for hierarchy. 184
Placement
- Tony F. Chan, Jason Cong, Kenton Sze:
Multilevel generalized force-directed method for circuit placement. 185-192 - Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris:
Unified quadratic programming approach for mixed mode placement. 193-199 - Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. 200-207 - Andrew B. Kahng, Sherief Reda:
Evaluation of placer suboptimality via zero-change netlist transformations. 208-215
2005 ISPD placement contest
- Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz:
The ISPD2005 placement contest and benchmark suite. 216-220 - Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
FastPlace: an analytical placer for mixed-mode designs. 221-223 - Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov:
Capo: robust and scalable open-source min-cut floorplacer. 224-226 - Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie:
mPL6: a robust multilevel mixed-size placement engine. 227-229 - Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden:
Recursive bisection placement: feng shui 5.0 implementation details. 230-232 - Andrew B. Kahng, Sherief Reda, Qinke Wang:
APlace: a general analytic placement framework. 233-235 - Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang:
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. 236-238 - Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska:
mFAR: fixed-points-addition-based VLSI placement algorithm. 239-241 - Bernd Obermeier, Hans Ranke, Frank M. Johannes:
Kraftwerk: a versatile placement approach. 242-244 - Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi:
Dragon2005: large-scale mixed-size placement tool. 245-247
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